Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/microarchitectures/tiger lake"
| Line 14: | Line 14: | ||
|speculative=Yes | |speculative=Yes | ||
|renaming=Yes | |renaming=Yes | ||
| − | |stages=14 | + | |stages min=14 |
| + | |stages max=19 | ||
|decode=5-way | |decode=5-way | ||
|isa=x86-64 | |isa=x86-64 | ||
Revision as of 11:26, 20 June 2021
| Edit Values | |
| Tiger Lake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | September 2, 2020 |
| Process | 10 nm |
| Core Configs | 2, 4, 6, 8 |
| Pipeline | |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 14-19 |
| Decode | 5-way |
| Instructions | |
| ISA | x86-64 |
| Cache | |
| L1I Cache | 32 KiB/core 8-way set associative |
| L1D Cache | 48 KiB/core 12-way associative |
| L2 Cache | 1280 KiB/core 20-way associative |
| L3 Cache | 3 MiB/core 12-way associative |
| Cores | |
| Core Names | Tiger Lake U, Tiger Lake H |
| Succession | |
| Contemporary | |
| Sapphire Rapids Rocket Lake | |
Tiger Lake (TGL) is Intel's successor to Ice Lake, a 10nm microarchitecture for mainstream workstations, desktops, and mobile devices.
Codenames
| Core | Abbrev | Description | Graphics | Target |
|---|---|---|---|---|
| Tiger Lake Y | TGL-Y | Extremely low power | 2-in-1s detachable, tablets, and computer sticks | |
| Tiger Lake U | TGL-U | Ultra-low Power | Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room | |
| Tiger Lake H35 | TGL-H35 | High-performance Graphics | 35W TDP. High mobile performance, mobile workstations | |
| Tiger Lake H | TGL-H | High-performance Graphics | 45W TDP. Ultimate mobile performance, mobile gaming, mobile workstations |
Process Technology
- Main article: Cannon Lake § Process Technology
Tiger Lake will be manufactured on Intel's third generation enhanced 10nm++ process.
History
Tiger Lake was first announced at Intel's 2019 Investor Meeting in May. Tiger Lake was said to succeed Ice Lake in 2020.
Architecture
Not much is known about Tiger Lake's architecture.
Key changes from Ice Lake
- Core
- Sunny Cove ➡ Willow Cove
- Up to 50% larger Level 3 cache - 3MB per core from 2MB per core
- 2,5x larger Level 2 cache - 1,25MB per core from 512KB per core
- GPU
- Display
- HDMI 2.1 (from HDMI 2.0b)
- I/O
- PCIe 4.0 (from 3.0)
- Hardware Telemetry
- Intel Platform Monitoring Technology provides access to hardware performance, sampling and tracing data.
Facts about "Tiger Lake - Microarchitectures - Intel"
| codename | Tiger Lake + |
| core count | 2 +, 4 +, 6 + and 8 + |
| designer | Intel + |
| first launched | September 2, 2020 + |
| full page name | intel/microarchitectures/tiger lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tiger Lake + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |