Difference between revisions of "amd/ryzen 9/4900h"

	Edit Values
	Ryzen 9 4900H
	General Info
Designer	AMD
Manufacturer	TSMC
Model Number	4900H
Market	Mobile
Introduction	March 16, 2020 (announced); March 16, 2020 (launched)
Shop	Amazon
	General Specs
Family	Ryzen 9
Series	4000
Locked	Yes
Frequency	3,300 MHz
Turbo Frequency	4,400 MHz
Clock multiplier	33
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Zen 2
Core Name	Renoir
Process	7 nm
Transistors	9,800,000,000
Technology	CMOS
Die	156 mm²
Word Size	64 bit
Cores	8
Threads	16
Max Memory	64 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Electrical
TDP	45 W
cTDP down	35 W
cTDP up	54 W
Tcase	0 °C – 105 °C
	Packaging
	Unknown package "amd,socket_fp6"

Revision as of 14:48, 9 May 2020

Ryzen 9 4900H is a 64-bit octa-core high-end performance x86 mobile microprocessor introduced by AMD in early 2020. Fabricated on TSMC's 7-nanometer process based on AMD's Zen 2 microarchitecture, the 4900H operates at a base frequency of 3.3 GHz with a TDP of 45 W and a Boost frequency of up to 4.4 GHz. This APU supports up to 64 GiB of DDR4-3200 or up to 32 GiB of quad-channel LPDDR4x-4266 memory. The 4900H integrates a Radeon Vega 8 Graphics operating at up to 1.75 GHz.

This model supports a configurable TDP-down of 35 W and TDP-up of 54 W.

The 4900HS is a lower-power version of this processor, featuring slightly lower base and turbo frequencies.

Cache

Main article: Zen 2 § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

512 KiB

524,288 B
0.5 MiB

L1I$	256 KiB 262,144 B 0.25 MiB	8x32 KiB	8-way set associative
L1D$	256 KiB 262,144 B 0.25 MiB	8x32 KiB	8-way set associative	write-back

L2$

4 MiB

4,096 KiB
4,194,304 B
0.00391 GiB

		8x512 KiB	8-way set associative	write-back

L3$

8 MiB

8,192 KiB
8,388,608 B
0.00781 GiB

		2x4 MiB

Memory controller

This SoC features two memory controllers, each supporting DDR4 or LPDDR4x. This chip supports up to 64 GiB of dual-channel DDR4 memory with data rates of up to 3200 MT/s (51.2 GB/s) or up to 32 GiB of quad-channel LPDDR4x with data rates of up to 4266 MT/s (68.27 GB/s).

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-3200, LPDDR4x-4266
Max Mem	64 GiB
Controllers	2
Channels	4
Max Bandwidth	68.27 GiB/s 69,908.48 MiB/s 73.304 GB/s 73,304.354 MB/s 0.0667 TiB/s 0.0733 TB/s
Bandwidth	Single 17.88 GiB/s Double 34.13 GB/s Quad 68.27 GB/s

Expansions

This processor has 16 PCIe lanes, 1x8 designated for a discrete GPU, 1x4 additional lanes for storage (e.g., NVMe), and 1x4 additional lanes reserved for additional peripherals (e.g., WiFi or LTE).

[Edit/Modify Expansions Info]

Expansion Options

PCIe	Revision: 3.0
	Max Lanes: 16
	Configuration: 1x8+1x4+1x4, 2x4+1x4+1x4

Graphics

[Edit/Modify IGP Info]

Integrated Graphics Information

GPU	Radeon Vega 8
Designer	AMD
Execution Units	8	Max Displays	4
Unified Shaders	512
Burst Frequency	1,750 MHz 1.75 GHz 1,750,000 KHz
Output	DP, HDMI

[Edit] Zen 2 with Radeon Vega Hardware Accelerated Video Capabilities
Codec	Encode	Decode
VP9 8bpc/10bpc		1080p240 4K 60 FPS
MPEG-2 (H.262) 8b	1080p240 4K 60 FPS	1080p480 4K 120 FPS
HEVC (H.265) 8bpc/10bpc	1080p240 4K 60 FPS	1080p240 4K 60 FPS

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
SSE4a	Streaming SIMD Extensions 4a
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
SHA	SHA Extensions
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
SMT	Simultaneous Multithreading
AMD-Vi	AMD-Vi (I/O MMU virtualization)
AMD-V	AMD Virtualization
SenseMI	SenseMI Technology

Die

Main article: Zen 2 § Die

Renoir microprocessors are fabricated on TSMC's 7-nanometer process. This SoC integrates 9.8 billion transistors on a single 156 mm² monolithic die which includes both the Zen 2 CPU cores along with the Vega GPU and various other additional components.

7-nanometer process (N7)
9,800,000,000 transistors
156 mm² die size

@@ Line 228: / Line 228: @@
 |amdpbod=No
 }}
+== Die ==
+{{amd renoir die}}

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Ryzen 9 4900H - AMD#pcie +
base frequency	3,300 MHz (3.3 GHz, 3,300,000 kHz) +
clock multiplier	33 +
core count	8 +
core name	Renoir +
designer	AMD +
die area	156 mm² (0.242 in², 1.56 cm², 156,000,000 µm²) +
family	Ryzen 9 +
first announced	March 16, 2020 +
first launched	March 16, 2020 +
full page name	amd/ryzen 9/4900h +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has amd amd-v technology	true +
has amd amd-vi technology	true +
has amd sensemi technology	true +
has ecc memory support	false +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has locked clock multiplier	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
integrated gpu	Radeon Vega 8 +
integrated gpu designer	AMD +
integrated gpu execution units	8 +
integrated gpu max frequency	1,750 MHz (1.75 GHz, 1,750,000 KHz) +
isa	x86-64 +
isa family	x86 +
l1$ size	512 KiB (524,288 B, 0.5 MiB) +
l1d$ description	8-way set associative +
l1d$ size	256 KiB (262,144 B, 0.25 MiB) +
l1i$ description	8-way set associative +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ description	8-way set associative +
l2$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldate	March 16, 2020 +
manufacturer	TSMC +
market segment	Mobile +
max case temperature	378.15 K (105 °C, 221 °F, 680.67 °R) +
max cpu count	1 +
max memory	65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth	68.27 GiB/s (69,908.48 MiB/s, 73.304 GB/s, 73,304.354 MB/s, 0.0667 TiB/s, 0.0733 TB/s) +
max memory channels	4 +
microarchitecture	Zen 2 +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	4900H +
name	Ryzen 9 4900H +
process	7 nm (0.007 μm, 7.0e-6 mm) +
series	4000 +
smp max ways	1 +
supported memory type	DDR4-3200 + and LPDDR4x-4266 +
tdp	45 W (45,000 mW, 0.0603 hp, 0.045 kW) +
tdp down	35 W (35,000 mW, 0.0469 hp, 0.035 kW) +
tdp up	54 W (54,000 mW, 0.0724 hp, 0.054 kW) +
technology	CMOS +
thread count	16 +
transistor count	9,800,000,000 +
turbo frequency	4,400 MHz (4.4 GHz, 4,400,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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