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{{tsmc title|Low-voltage-In-Package-INterCONnect (LIPINCON)}}{{interconnect arch}} | {{tsmc title|Low-voltage-In-Package-INterCONnect (LIPINCON)}}{{interconnect arch}} | ||
'''Low-voltage-In-Package-INterCONnect''' ('''LIPINCON''') is a proprietary system [[interconnect architecture]] that facilitates data transmission across all linked components. | '''Low-voltage-In-Package-INterCONnect''' ('''LIPINCON''') is a proprietary system [[interconnect architecture]] that facilitates data transmission across all linked components. | ||
| + | |||
| + | == Overview == | ||
| + | LIPINCON is an interconnect architecture designed for [[chiplet]] designs with advanced packaging technologies such as {{tsmc|InFO}} and {{tsmc|CoWoS}}. LIPINCON uses a timing compensation mechanism in order to achieve a low-power and small area slave PHY (e.g., memory die or a transceiver die) while excluding the PLL/DLL but retaining good timing margins. | ||
| + | |||
| + | == Bibliography == | ||
| + | * TSMC, MS Lin et a., 2013 VLSI Symposium | ||
Revision as of 12:29, 22 June 2019
| Interconnect Architectures | |
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| Concepts | |
| General | |
| Peripheral | |
| Storage Devices | |
| Audio Devices | |
Low-voltage-In-Package-INterCONnect (LIPINCON) is a proprietary system interconnect architecture that facilitates data transmission across all linked components.
Overview
LIPINCON is an interconnect architecture designed for chiplet designs with advanced packaging technologies such as InFO and CoWoS. LIPINCON uses a timing compensation mechanism in order to achieve a low-power and small area slave PHY (e.g., memory die or a transceiver die) while excluding the PLL/DLL but retaining good timing margins.
Bibliography
- TSMC, MS Lin et a., 2013 VLSI Symposium