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(Cascade Lake W Processors)
(Overview)
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== Overview ==
 
== Overview ==
Cascade La W are enterprise workstation microprocessors. Those are a two-chip solution consisting of the microprocessor and the ? chipset. All processors are socket ?, manufactured on Intel's [[14 nm process|enhanced 14++ nm process]] based on the {{intel|Cascade Lake|Skylake|l=arch}} microarchitecture. Those are single-socket chips only. Geared toward business workstations, those processors come with all the related features such as {{intel|vPro}}, {{intel|Volume Management Device}} (VMD), and RAS.
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Cascade La W are enterprise workstation microprocessors. Those are a two-chip solution consisting of the microprocessor and the {{intel|Lewisburg|l=chipset}} chipset. All processors are socket {{intel|FCLGA-3647}}, manufactured on Intel's [[14 nm process|enhanced 14++ nm process]] based on the {{intel|Cascade Lake|Skylake|l=arch}} microarchitecture. Those are single-socket chips only. Geared toward business workstations, those processors come with all the related features such as {{intel|vPro}}, {{intel|Volume Management Device}} (VMD), and RAS.
  
 
=== Common Features ===
 
=== Common Features ===
 
For the most part, Cascade Lake W processors come with all the features enabled and only [[core count]] and {{intel|frequency behavior|frequency}} being the differentiating feature. It's worth pointing out that the Skylake W come with {{x86|AVX-512}} along with two full execution units, similar to the high-end {{intel|Skylake SP|l=core}} models (with the exception of the two low-end models). All models have 48 [[PCIe]] lanes and have all the following features in common:
 
For the most part, Cascade Lake W processors come with all the features enabled and only [[core count]] and {{intel|frequency behavior|frequency}} being the differentiating feature. It's worth pointing out that the Skylake W come with {{x86|AVX-512}} along with two full execution units, similar to the high-end {{intel|Skylake SP|l=core}} models (with the exception of the two low-end models). All models have 48 [[PCIe]] lanes and have all the following features in common:
  
* '''Mem:''' 512 GiB of quad-channel DDR4-2933 ECC Memory
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* '''Mem:''' 1 TiB of quad-channel DDR4-2933 ECC Memory
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** ''M'' models support 2 TiB of memory
 
** DPC RDIMM and LRDIMM \w [[ECC]]
 
** DPC RDIMM and LRDIMM \w [[ECC]]
 
* '''I/O:''' 48 [[PCIe]] 3.0 Lanes
 
* '''I/O:''' 48 [[PCIe]] 3.0 Lanes
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* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}})
 
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}})
 
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|TBT 2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Identity Protection}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|Volume Management Device}} (VMD).
 
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|TBT 2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Identity Protection}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|Volume Management Device}} (VMD).
 
  
 
== Cascade Lake W Processors ==
 
== Cascade Lake W Processors ==

Revision as of 19:43, 3 June 2019

Edit Values
Cascade Lake W
General Info
DesignerIntel
ManufacturerIntel
IntroductionJune 3, 2019 (announced)
June 3, 2019 (launched)
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformGlacier Falls
Word Size
8 octets
16 nibbles
64 bit
Process14 nm
0.014 μm
1.4e-5 mm
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Cascade Lake W (Cascade Lake Workstations; CLS-W) is codename for Intel's enterprise workstation microprocessor line based on the Cascade Lake microarchitecture, succeeding Skylake W. Cascade Lake W processors feature a number of enhancements including a new AVX512 x86 extension for neural network / deep learning workloads, and introduces persistent memory support. Cascade Lake W series of processors are branded as the Xeon W family.

Overview

Cascade La W are enterprise workstation microprocessors. Those are a two-chip solution consisting of the microprocessor and the Lewisburg chipset. All processors are socket FCLGA-3647, manufactured on Intel's enhanced 14++ nm process based on the Skylake microarchitecture. Those are single-socket chips only. Geared toward business workstations, those processors come with all the related features such as vPro, Volume Management Device (VMD), and RAS.

Common Features

For the most part, Cascade Lake W processors come with all the features enabled and only core count and frequency being the differentiating feature. It's worth pointing out that the Skylake W come with AVX-512 along with two full execution units, similar to the high-end Skylake SP models (with the exception of the two low-end models). All models have 48 PCIe lanes and have all the following features in common:

Cascade Lake W Processors

Note that for the lower core-count models, the L3 cache size is larger than it would otherwise be due to additional cache slices being enabled from disabled cores.

 List of Cascade Lake W-based Processors
ModelLaunchedPriceCoresThreadsTDPL2L3FrequencyTurboAVX-512 Units
Count: 0

See also

arrow up 1.svgPower/Performance

designerIntel +
first announcedJune 3, 2019 +
first launchedJune 3, 2019 +
instance ofcore +
isax86-64 +
isa familyx86 +
manufacturerIntel +
microarchitectureCascade Lake +
nameCascade Lake W +
packageFCLGA-3647 +
platformGlacier Falls +
process14 nm (0.014 μm, 1.4e-5 mm) +
socketSocket P + and LGA-3647 +
word size64 bit (8 octets, 16 nibbles) +