From WikiChip
Difference between revisions of "intel/cores/cascade lake w"
< intel

Line 2: Line 2:
 
{{core
 
{{core
 
|name=Cascade Lake W
 
|name=Cascade Lake W
 +
|no image=Yes
 
|developer=Intel
 
|developer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel

Revision as of 12:06, 3 June 2019

Edit Values
Cascade Lake W
General Info
DesignerIntel
ManufacturerIntel
Introduction2019 (announced)
2019 (launched)
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformGlacier Falls
Word Size
8 octets
16 nibbles
64 bit
Process14 nm
0.014 μm
1.4e-5 mm
Succession

Cascade Lake W (Cascade Lake Workstations; CLS-W) is codename for Intel's enterprise workstation microprocessor line based on the Cascade Lake microarchitecture, succeeding Skylake W. Cascade Lake W processors feature a number of enhancements including a new AVX512 x86 extension for neural network / deep learning workloads, and introduces persistent memory support. Cascade Lake W series of processors are branded as the Xeon W family.

Overview

Cascade La W are enterprise workstation microprocessors. Those are a two-chip solution consisting of the microprocessor and the ? chipset. All processors are socket ?, manufactured on Intel's enhanced 14++ nm process based on the Skylake microarchitecture. Those are single-socket chips only. Geared toward business workstations, those processors come with all the related features such as vPro, Volume Management Device (VMD), and RAS.

Common Features

For the most part, Cascade Lake W processors come with all the features enabled and only core count and frequency being the differentiating feature. It's worth pointing out that the Skylake W come with AVX-512 along with two full execution units, similar to the high-end Skylake SP models (with the exception of the two low-end models). All models have 48 PCIe lanes and have all the following features in common:


Cascade Lake W Processors

Note that for the lower core-count models, the L3 cache size is larger than it would otherwise be due to additional cache slices being enabled from disabled cores.

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
 List of Cascade Lake W-based Processors
ModelLaunchedPriceCoresThreadsTDPL2L3FrequencyTurboAVX-512 Units
Count: 0

See also

arrow up 1.svgPower/Performance

designerIntel +
first announcedOctober 7, 2019 +
first launchedOctober 7, 2019 +
instance ofcore +
isax86-64 +
isa familyx86 +
main imageFile:cascade-lake-w (front).png +
manufacturerIntel +
microarchitectureCascade Lake +
nameCascade Lake W +
packageFCLGA-2066 +
platformGlacier Falls +
process14 nm (0.014 μm, 1.4e-5 mm) +
socketSocket R4 +
word size64 bit (8 octets, 16 nibbles) +