Revision as of 12:05, 3 June 2019

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Cascade Lake W
General Info
Designer	Intel
Manufacturer	Intel
Introduction	2019 (announced) 2019 (launched)
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cascade Lake
Platform	Glacier Falls
Word Size	8 octets 16 nibbles 64 bit
Process	14 nm 0.014 μm 1.4e-5 mm
Succession
Skylake W

Cascade Lake W (Cascade Lake Workstations; CLS-W) is codename for Intel's enterprise workstation microprocessor line based on the Cascade Lake microarchitecture, succeeding Skylake W. Cascade Lake W processors feature a number of enhancements including a new AVX512 x86 extension for neural network / deep learning workloads, and introduces persistent memory support. Cascade Lake W series of processors are branded as the Xeon W family.

Overview

Cascade La W are enterprise workstation microprocessors. Those are a two-chip solution consisting of the microprocessor and the ? chipset. All processors are socket ?, manufactured on Intel's enhanced 14++ nm process based on the Skylake microarchitecture. Those are single-socket chips only. Geared toward business workstations, those processors come with all the related features such as vPro, Volume Management Device (VMD), and RAS.

Common Features

For the most part, Cascade Lake W processors come with all the features enabled and only core count and frequency being the differentiating feature. It's worth pointing out that the Skylake W come with AVX-512 along with two full execution units, similar to the high-end Skylake SP models (with the exception of the two low-end models). All models have 48 PCIe lanes and have all the following features in common:

• Mem: 512 GiB of quad-channel DDR4-2933 ECC Memory
  • DPC RDIMM and LRDIMM \w ECC
• I/O: 48 PCIe 3.0 Lanes
• TDP: 160 W - 205 W
• ISA: Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX-512-F/CD/BW/DQ/VL/VNNI)
• Features: Speed Shift, vPro, VT-x/EPT, VT-d, TBT 2.0, TSX, TXT, SpeedStep, Identity Protection, Secure Key, MPX, OS Guard, and Volume Management Device (VMD).

Cascade Lake W Processors

Note that for the lower core-count models, the L3 cache size is larger than it would otherwise be due to additional cache slices being enabled from disabled cores.

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

See also