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{{intel title|Xeon Gold 6252}}
 
{{intel title|Xeon Gold 6252}}
{{chip}}
+
{{chip
 +
|name=Xeon Gold 6252
 +
|image=cascade lake sp (front).png
 +
|designer=Intel
 +
|manufacturer=Intel
 +
|model number=6252
 +
|part number=CD8069504194401
 +
|s-spec=SRF91
 +
|market=Server
 +
|first announced=April 2, 2019
 +
|first launched=April 2, 2019
 +
|release price (tray)=$3,655.00
 +
|release price (box)=$3,662.00
 +
|family=Xeon Gold
 +
|series=6200
 +
|locked=Yes
 +
|frequency=2,100 MHz
 +
|turbo frequency1=3,700 MHz
 +
|bus type=DMI 3.0
 +
|bus links=4
 +
|bus rate=8 GT/s
 +
|clock multiplier=21
 +
|isa=x86-64
 +
|isa family=x86
 +
|microarch=Cascade Lake
 +
|platform=Purley
 +
|chipset=Lewisburg
 +
|core name=Cascade Lake SP
 +
|core family=6
 +
|core model=85
 +
|process=14 nm
 +
|technology=CMOS
 +
|word size=64 bit
 +
|core count=24
 +
|thread count=48
 +
|max cpus=4
 +
|max memory=1 TiB
 +
|tdp=150 W
 +
|tcase min=0 °C
 +
|tcase max=86 °C
 +
|package name 1=intel,fclga_3647
 +
}}
 
'''Xeon Gold 6252''' is a {{arch|64}} [[24-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6252 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 150 W and features a {{intel|turbo boost}} frequency of up to 3.7 GHz.
 
'''Xeon Gold 6252''' is a {{arch|64}} [[24-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6252 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 150 W and features a {{intel|turbo boost}} frequency of up to 3.7 GHz.
  

Revision as of 23:44, 7 May 2019

Edit Values
Xeon Gold 6252
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number6252
Part NumberCD8069504194401
S-SpecSRF91
MarketServer
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
Release Price$3,655.00 (tray)
$3,662.00 (box)
ShopAmazon
General Specs
FamilyXeon Gold
Series6200
LockedYes
Frequency2,100 MHz
Turbo Frequency3,700 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier21
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Core Model85
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores24
Threads48
Max Memory1 TiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
Electrical
TDP150 W
Tcase0 °C – 86 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647

Xeon Gold 6252 is a 64-bit 24-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6252 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 150 W and features a turbo boost frequency of up to 3.7 GHz.


Cache

Main article: Cascade Lake § Cache

The Xeon Gold 6252 features a larger non-default 35.75 MiB of L3, a size that would normally be found on a 26-core part.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.5 MiB
1,536 KiB
1,572,864 B
L1I$768 KiB
786,432 B
0.75 MiB
24x32 KiB8-way set associative 
L1D$768 KiB
786,432 B
0.75 MiB
24x32 KiB8-way set associativewrite-back

L2$24 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
  24x1 MiB16-way set associativewrite-back

L3$35.75 MiB
36,608 KiB
37,486,592 B
0.0349 GiB
  26x1.375 MiB11-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2933
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth131.13 GiB/s
134,277.12 MiB/s
140.8 GB/s
140,799.765 MB/s
0.128 TiB/s
0.141 TB/s
Bandwidth
Single 21.86 GiB/s
Double 43.71 GiB/s
Quad 87.42 GiB/s
Hexa 131.13 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: 1x16, x8, x4


Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
DL BoostDeep Learning Boost
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 6252 - Intel#pcie +
full page nameintel/xeon gold/6252 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost +
has intel deep learning boosttrue +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
l1$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description8-way set associative +
l1d$ size768 KiB (786,432 B, 0.75 MiB) +
l1i$ description8-way set associative +
l1i$ size768 KiB (786,432 B, 0.75 MiB) +
l2$ description16-way set associative +
l2$ size24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) +
l3$ description11-way set associative +
l3$ size35.75 MiB (36,608 KiB, 37,486,592 B, 0.0349 GiB) +
ldate1900 +
max memory bandwidth131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) +
max memory channels6 +
supported memory typeDDR4-2933 +