From WikiChip
Difference between revisions of "intel/xeon gold/6246"
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|l3 desc=11-way set associative | |l3 desc=11-way set associative | ||
|l3 policy=write-back | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2933 | ||
+ | |ecc=Yes | ||
+ | |max mem=1 TiB | ||
+ | |controllers=2 | ||
+ | |channels=6 | ||
+ | |max bandwidth=131.13 GiB/s | ||
+ | |bandwidth schan=21.86 GiB/s | ||
+ | |bandwidth dchan=43.71 GiB/s | ||
+ | |bandwidth qchan=87.42 GiB/s | ||
+ | |bandwidth hchan=131.13 GiB/s | ||
}} | }} |
Revision as of 22:42, 7 May 2019
Edit Values | |
General Info | |
Microarchitecture |
Xeon Gold 6246 is a 64-bit 12-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6246 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.3 GHz with a TDP of 165 W and features a turbo boost frequency of up to 4.2 GHz.
Cache
- Main article: Cascade Lake § Cache
The Xeon Gold 6246 features a considerably larger non-default 24.75 MiB of L3, a size that would normally be found on an 18-core part.
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Facts about "Xeon Gold 6246 - Intel"
full page name | intel/xeon gold/6246 + |
has ecc memory support | true + |
instance of | microprocessor + |
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) + |
ldate | 1900 + |
max memory bandwidth | 131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) + |
max memory channels | 6 + |
supported memory type | DDR4-2933 + |