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| | {{intel title|Xeon Gold 6230}} | | {{intel title|Xeon Gold 6230}} |
| − | {{chip | + | {{chip}} |
| − | |name=Xeon Gold 6230
| + | '''Xeon Gold 6230''' is a {{arch|64}} [[20-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6230 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 125 W and features a {{intel|turbo boost}} frequency of up to 3.9 GHz. |
| − | |image=skylake sp (basic).png
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| − | |designer=Intel
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| − | |manufacturer=Intel
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| − | |model number=6230
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| − | |market=Server
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| − | |first announced=March, 2019
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| − | |first launched=March, 2019
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| − | |family=Xeon Gold
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| − | |series=6000
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| − | |locked=Yes
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| − | |frequency=2,100 MHz
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| − | |turbo frequency1=3,900 MHz
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| − | |bus type=DMI 3.0
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| − | |bus links=4
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| − | |bus rate=8 GT/s
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| − | |clock multiplier=21
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| − | |cpuid=0x50655
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| − | |isa=x86-64
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| − | |isa family=x86
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| − | |microarch=Cascade Lake
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| − | |platform=Purley
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| − | |chipset=Lewisburg
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| − | |core name=Cascade Lake SP
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| − | |core family=6
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| − | |process=14 nm
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| − | |technology=CMOS
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| − | |word size=64 bit
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| − | |core count=20
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| − | |thread count=40
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| − | |max cpus=4
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| − | |tdp=125 W
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| − | |package module 1={{packages/intel/fclga-3647}}
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| − | }} | |
| − | '''Xeon Gold 6230''' is a {{arch|64}} [[20-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6230 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory and persistent memory, operates at 2.1 GHz with a TDP of 125 W and features a {{intel|turbo boost}} frequency of up to 3.9 GHz. | |
| − | | |
| − | | |
| − | == Cache ==
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| − | {{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
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| − | {{cache size
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| − | |l1 cache=1.25 MiB
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| − | |l1i cache=640 KiB
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| − | |l1i break=20x32 KiB
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| − | |l1i desc=8-way set associative
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| − | |l1d cache=640 KiB
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| − | |l1d break=20x32 KiB
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| − | |l1d desc=8-way set associative
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| − | |l1d policy=write-back
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| − | |l2 cache=20 MiB
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| − | |l2 break=20x1 MiB
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| − | |l2 desc=16-way set associative
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| − | |l2 policy=write-back
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| − | |l3 cache=27.5 MiB
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| − | |l3 break=20x1.375 MiB
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| − | |l3 desc=11-way set associative
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| − | |l3 policy=write-back
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| − | }}
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| − | | |
| − | == Memory controller ==
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| − | {{memory controller
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| − | |type=DDR4-2933
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| − | |ecc=Yes
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| − | |max mem=1 TiB
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| − | |controllers=2
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| − | |channels=6
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| − | |max bandwidth=140.76 GiB/s
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| − | |bandwidth schan=23.46 GiB/s
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| − | |bandwidth dchan=46.92 GiB/s
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| − | |bandwidth qchan=93.84 GiB/s
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| − | |bandwidth hchan=140.76 GiB/s
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| − | }}
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| − | | |
| − | == Expansions ==
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| − | {{expansions
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| − | | pcie revision = 3.0
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| − | | pcie lanes = 48
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| − | | pcie config = x16
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| − | | pcie config 2 = x8
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| − | | pcie config 3 = x4
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| − | }}
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| − | | |
| − | == Features ==
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| − | {{x86 features
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| − | |real=Yes
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| − | |protected=Yes
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| − | |smm=Yes
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| − | |fpu=Yes
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| − | |x8616=Yes
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| − | |x8632=Yes
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| − | |x8664=Yes
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| − | |nx=Yes
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| − | |mmx=Yes
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| − | |emmx=Yes
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| − | |sse=Yes
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| − | |sse2=Yes
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| − | |sse3=Yes
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| − | |ssse3=Yes
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| − | |sse41=Yes
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| − | |sse42=Yes
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| − | |sse4a=No
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| − | |avx=Yes
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| − | |avx2=Yes
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| − | |avx512f=Yes
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| − | |avx512cd=Yes
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| − | |avx512er=No
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| − | |avx512pf=No
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| − | |avx512bw=Yes
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| − | |avx512dq=Yes
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| − | |avx512vl=Yes
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| − | |avx512ifma=No
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| − | |avx512vbmi=No
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| − | |avx5124fmaps=No
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| − | |avx512vnni=Yes
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| − | |avx5124vnniw=No
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| − | |avx512vpopcntdq=No
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| − | |abm=Yes
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| − | |tbm=No
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| − | |bmi1=Yes
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| − | |bmi2=Yes
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| − | |fma3=Yes
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| − | |fma4=No
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| − | |aes=Yes
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| − | |rdrand=Yes
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| − | |sha=No
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| − | |xop=No
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| − | |adx=Yes
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| − | |clmul=Yes
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| − | |f16c=Yes
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| − | |bfloat16=No
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| − | |tbt1=No
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| − | |tbt2=Yes
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| − | |tbmt3=No
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| − | |bpt=No
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| − | |eist=Yes
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| − | |sst=Yes
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| − | |flex=No
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| − | |fastmem=No
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| − | |ivmd=Yes
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| − | |intelnodecontroller=Yes
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| − | |intelnode=Yes
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| − | |kpt=Yes
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| − | |ptt=Yes
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| − | |intelrunsure=Yes
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| − | |mbe=Yes
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| − | |isrt=No
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| − | |sba=No
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| − | |mwt=No
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| − | |sipp=No
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| − | |att=No
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| − | |ipt=No
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| − | |tsx=Yes
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| − | |txt=Yes
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| − | |ht=Yes
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| − | |vpro=Yes
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| − | |vtx=Yes
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| − | |vtd=Yes
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| − | |ept=Yes
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| − | |mpx=No
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| − | |sgx=No
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| − | |securekey=No
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| − | |osguard=No
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| − | |intqat=No
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| − | |dlboost=Yes
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| − | |3dnow=No
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| − | |e3dnow=No
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| − | |smartmp=No
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| − | |powernow=No
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| − | |amdvi=No
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| − | |amdv=No
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| − | |amdsme=No
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| − | |amdtsme=No
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| − | |amdsev=No
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| − | |rvi=No
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| − | |smt=No
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| − | |sensemi=No
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| − | |xfr=No
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| − | |xfr2=No
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| − | |mxfr=No
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| − | |amdpb=No
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| − | |amdpb2=No
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| − | |amdpbod=No
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| − | }}
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| − | | |
| − | | |
| − | == Frequencies ==
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| − | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
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| − | {{frequency table
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| − | |freq_base=2,100 MHz
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| − | |freq_1=3,900 MHz
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| − | |freq_2=3,900 MHz
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| − | |freq_3=3,700 MHz
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| − | |freq_4=3,700 MHz
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| − | |freq_5=3,600 MHz
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| − | |freq_6=3,600 MHz
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| − | |freq_7=3,600 MHz
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| − | |freq_8=3,600 MHz
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| − | |freq_9=3,400 MHz
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| − | |freq_10=3,400 MHz
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| − | |freq_11=3,400 MHz
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| − | |freq_12=3,400 MHz
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| − | |freq_13=3,000 MHz
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| − | |freq_14=3,000 MHz
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| − | |freq_15=3,000 MHz
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| − | |freq_16=3,000 MHz
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| − | |freq_17=2,800 MHz
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| − | |freq_18=2,800 MHz
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| − | |freq_19=2,800 MHz
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| − | |freq_20=2,800 MHz
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| − | |freq_avx2_base=1,600 MHz
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| − | |freq_avx2_1=3,800 MHz
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| − | |freq_avx2_2=3,800 MHz
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| − | |freq_avx2_3=3,600 MHz
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| − | |freq_avx2_4=3,600 MHz
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| − | |freq_avx2_5=3,400 MHz
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| − | |freq_avx2_6=3,400 MHz
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| − | |freq_avx2_7=3,400 MHz
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| − | |freq_avx2_8=3,400 MHz
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| − | |freq_avx2_9=2,900 MHz
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| − | |freq_avx2_10=2,900 MHz
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| − | |freq_avx2_11=2,900 MHz
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| − | |freq_avx2_12=2,900 MHz
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| − | |freq_avx2_13=2,600 MHz
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| − | |freq_avx2_14=2,600 MHz
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| − | |freq_avx2_15=2,600 MHz
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| − | |freq_avx2_16=2,600 MHz
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| − | |freq_avx2_17=2,400 MHz
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| − | |freq_avx2_18=2,400 MHz
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| − | |freq_avx2_19=2,400 MHz
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| − | |freq_avx2_20=2,400 MHz
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| − | |freq_avx512_base=1,100 MHz
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| − | |freq_avx512_1=3,700 MHz
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| − | |freq_avx512_2=3,700 MHz
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| − | |freq_avx512_3=3,500 MHz
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| − | |freq_avx512_4=3,500 MHz
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| − | |freq_avx512_5=2,800 MHz
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| − | |freq_avx512_6=2,800 MHz
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| − | |freq_avx512_7=2,800 MHz
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| − | |freq_avx512_8=2,800 MHz
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| − | |freq_avx512_9=2,400 MHz
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| − | |freq_avx512_10=2,400 MHz
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| − | |freq_avx512_11=2,400 MHz
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| − | |freq_avx512_12=2,400 MHz
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| − | |freq_avx512_13=2,100 MHz
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| − | |freq_avx512_14=2,100 MHz
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| − | |freq_avx512_15=2,100 MHz
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| − | |freq_avx512_16=2,100 MHz
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| − | |freq_avx512_17=2,000 MHz
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| − | |freq_avx512_18=2,000 MHz
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| − | |freq_avx512_19=2,000 MHz
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| − | |freq_avx512_20=2,000 MHz
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| − | }}
| |
Revision as of 20:27, 7 May 2019
Xeon Gold 6230 is a 64-bit 20-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6230 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 125 W and features a turbo boost frequency of up to 3.9 GHz.
