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Difference between revisions of "intel/xeon platinum/9221"
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{{intel title|Xeon Platinum 9221}}
 
{{intel title|Xeon Platinum 9221}}
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{{chip}}
+
{{chip
 +
|name=Xeon Platinum 9221
 +
|image=cascade lake ap (front).png
 +
|designer=Intel
 +
|manufacturer=Intel
 +
|model number=9221
 +
|market=Server
 +
|market 2=HPC
 +
|first announced=April 2, 2019
 +
|first launched=April 2, 2019
 +
|family=Xeon Platinum
 +
|series=9200
 +
|locked=Yes
 +
|frequency=2,100 MHz
 +
|turbo frequency1=3,700 MHz
 +
|bus type=DMI 3.0
 +
|bus links=4
 +
|bus rate=8 GT/s
 +
|clock multiplier=21
 +
|isa=x86-64
 +
|isa family=x86
 +
|microarch=Cascade Lake
 +
|platform=Walker Pass
 +
|chipset=Lewisburg
 +
|core name=Cascade Lake AP
 +
|core family=6
 +
|process=14 nm
 +
|technology=CMOS
 +
|mcp=Yes
 +
|die count=2
 +
|word size=64 bit
 +
|core count=32
 +
|thread count=64
 +
|max cpus=2
 +
|max memory=2 TiB
 +
|tdp=250 W
 +
|package name 1=intel,fcbga_5903
 +
}}
 
'''Xeon Platinum 9221''' is a [[56-core]] {{arch|64}} high-performance [[x86]] server microprocessor introduced by Intel in early [[2019]]. The 9221 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is fabricated on Intel's [[14 nm process]]. It operates at 2.1 GHz with a TDP of 250 W and a {{intel|turbo boost}} of up to 3.7 GHz. This processor supports up to twelve channels of DDR4-2933 memory.
 
'''Xeon Platinum 9221''' is a [[56-core]] {{arch|64}} high-performance [[x86]] server microprocessor introduced by Intel in early [[2019]]. The 9221 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is fabricated on Intel's [[14 nm process]]. It operates at 2.1 GHz with a TDP of 250 W and a {{intel|turbo boost}} of up to 3.7 GHz. This processor supports up to twelve channels of DDR4-2933 memory.

Revision as of 14:32, 2 April 2019

Edit Values
Xeon Platinum 9221
cascade lake ap (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number9221
MarketServer, HPC
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
ShopAmazon
General Specs
FamilyXeon Platinum
Series9200
LockedYes
Frequency2,100 MHz
Turbo Frequency3,700 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier21
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformWalker Pass
ChipsetLewisburg
Core NameCascade Lake AP
Core Family6
Process14 nm
TechnologyCMOS
MCPYes (2 dies)
Word Size64 bit
Cores32
Threads64
Max Memory2 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
TDP250 W
Packaging
PackageFCBGA-5903 (BGA)
Pitch0.99 mm
Contacts5903

Xeon Platinum 9221 is a 56-core 64-bit high-performance x86 server microprocessor introduced by Intel in early 2019. The 9221 is based on the Cascade Lake microarchitecture and is fabricated on Intel's 14 nm process. It operates at 2.1 GHz with a TDP of 250 W and a turbo boost of up to 3.7 GHz. This processor supports up to twelve channels of DDR4-2933 memory.

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_platinum/9221&oldid=87781"
Facts about "Xeon Platinum 9221 - Intel"
RDF feed
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier21 +
core count32 +
core family6 +
core nameCascade Lake AP +
designerIntel +
die count2 +
familyXeon Platinum +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon platinum/9221 +
has locked clock multipliertrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
ldateApril 2, 2019 +
main imageFile:cascade lake ap (front).png +
manufacturerIntel +
market segmentServer + and HPC +
max cpu count2 +
max memory2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
microarchitectureCascade Lake +
model number9221 +
nameXeon Platinum 9221 +
packageFCBGA-5903 +
platformWalker Pass +
process14 nm (0.014 μm, 1.4e-5 mm) +
series9200 +
smp max ways2 +
tdp250 W (250,000 mW, 0.335 hp, 0.25 kW) +
technologyCMOS +
thread count64 +
turbo frequency (1 core)3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +