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Difference between revisions of "intel/xeon d/d-1521"
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== Networking ==
 
== Networking ==
{{soc networking
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{{network
| SFI interface    = Yes
+
|eth opts=Yes
| KR interface      = Yes
+
|10ge=Yes
| KR4 interface    = No
+
|10ge ports=2
| KX interface      = Yes
 
| KX4 interface    = No
 
| 10Base-T          = No
 
| 100Base-T        = No
 
| 1000Base-T        = Yes
 
| 10GBase-T        = Yes
 
 
}}
 
}}
  

Revision as of 01:00, 1 April 2019

Edit Values
Xeon D-1521
broadwell de (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberD-1521
Part NumberGG8067402568800
S-SpecSR2DF
QJPX (QS)
MarketServer
IntroductionNovember 1, 2015 (announced)
November 1, 2015 (launched)
Release Price$199.00 (tray)
ShopAmazon
General Specs
FamilyXeon D
SeriesD-1500
LockedYes
Frequency2,400 MHz
Turbo Frequency2,700 MHz (1 core)
Bus typeDMI 2.0
Clock multiplier24
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureBroadwell
PlatformGrangeville
Core NameBroadwell DE
Core Family6
Core Model6
Core SteppingV2
Process14 nm
Transistors3,200,000,000
TechnologyCMOS
Die246.24 mm²
Word Size64 bit
Cores4
Threads8
Max Memory128 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP45 W
OP Temperature0 °C – 108 °C
Packaging
PackageFCBGA-1667 (FCBGA)
Dimension37.5 mm × 37.5 mm × 3.557 mm
Pitch0.7 mm
Contacts1667
broadwell de (back).png

Xeon D-1521 is a 64-bit quad-core x86 microserver SoC introduced by Intel in late 2015. The D-1521 is based on the Broadwell microarchitecture and is fabricated on their 14 nm process. It operates at 2.4 GHz with a TDP of 45 W and a turbo frequency of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.


Cache

Main article: Broadwell § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back

L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB8-way set associativewrite-back

L3$6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
  4x1.5 MiB16-way set associativewrite-back

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Max Mem128 GiB
Controllers1
Channels2
Max Bandwidth31.78 GiB/s
32,542.72 MiB/s
34.124 GB/s
34,123.515 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.78 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes8
Configsx4, x16
USB
Revision2.0, 3.0
Ports8
UART

Integrated LANYes


Networking

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
Ethernet
10GbEYes (Ports: 2)

Features

Facts about "Xeon D-1521 - Intel"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon D-1521 - Intel#io +
back imageFile:broadwell de (back).png +
base frequency2,400 MHz (2.4 GHz, 2,400,000 kHz) +
bus typeDMI 2.0 +
clock multiplier24 +
core count4 +
core family6 +
core model6 +
core nameBroadwell DE +
core steppingV2 +
designerIntel +
die area246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) +
familyXeon D +
first announcedNovember 1, 2015 +
first launchedNovember 1, 2015 +
full page nameintel/xeon d/d-1521 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has locked clock multipliertrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description16-way set associative +
l3$ size6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +
ldateNovember 1, 2015 +
main imageFile:broadwell de (front).png +
manufacturerIntel +
market segmentServer +
max cpu count1 +
max memory131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) +
max memory bandwidth31.78 GiB/s (32,542.72 MiB/s, 34.124 GB/s, 34,123.515 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max operating temperature108 °C +
max pcie lanes8 +
microarchitectureBroadwell +
min operating temperature0 °C +
model numberD-1521 +
nameXeon D-1521 +
packageFCBGA-1667 +
part numberGG8067402568800 +
platformGrangeville +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 199.00 (€ 179.10, £ 161.19, ¥ 20,562.67) +
release price (tray)$ 199.00 (€ 179.10, £ 161.19, ¥ 20,562.67) +
s-specSR2DF +
s-spec (qs)QJPX +
seriesD-1500 +
smp max ways1 +
supported memory typeDDR4-2133 +
tdp45 W (45,000 mW, 0.0603 hp, 0.045 kW) +
technologyCMOS +
thread count8 +
transistor count3,200,000,000 +
turbo frequency (1 core)2,700 MHz (2.7 GHz, 2,700,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +