From WikiChip
Difference between revisions of "intel/xeon d/d-1541"
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== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}} | + | {{main|intel/microarchitectures/broadwell (server)#Memory_Hierarchy|l1=Broadwell § Cache}} |
− | {{cache | + | {{cache size |
+ | |l1 cache=512 KiB | ||
|l1i cache=256 KiB | |l1i cache=256 KiB | ||
|l1i break=8x32 KiB | |l1i break=8x32 KiB | ||
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
− | |||
|l1d cache=256 KiB | |l1d cache=256 KiB | ||
|l1d break=8x32 KiB | |l1d break=8x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
− | |l1d | + | |l1d policy=write-back |
|l2 cache=2 MiB | |l2 cache=2 MiB | ||
|l2 break=8x256 KiB | |l2 break=8x256 KiB | ||
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
− | |l2 | + | |l2 policy=write-back |
|l3 cache=12 MiB | |l3 cache=12 MiB | ||
|l3 break=8x1.5 MiB | |l3 break=8x1.5 MiB | ||
− | |l3 | + | |l3 desc=16-way set associative |
+ | |l3 policy=write-back | ||
}} | }} | ||
Revision as of 01:10, 1 April 2019
Edit Values | |
Xeon D-1541 | |
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General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | D-1541 |
Part Number | GG8067402568700 |
S-Spec | SR2DE QJPW (QS) |
Market | Server |
Introduction | November 1, 2015 (announced) November 1, 2015 (launched) |
Release Price | $581.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon D |
Series | D-1500 |
Locked | Yes |
Frequency | 2,100 MHz |
Turbo Frequency | 2,700 MHz (1 core) |
Bus type | DMI 2.0 |
Clock multiplier | 21 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Broadwell |
Platform | Grangeville |
Core Name | Broadwell DE |
Core Family | 6 |
Core Model | 6 |
Core Stepping | V2 |
Process | 14 nm |
Transistors | 3,200,000,000 |
Technology | CMOS |
Die | 246.24 mm² |
Word Size | 64 bit |
Cores | 8 |
Threads | 16 |
Max Memory | 128 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 45 W |
OP Temperature | 0 °C – 108 °C |
Packaging | |
Package | FCBGA-1667 (FCBGA) |
Dimension | 37.5 mm × 37.5 mm × 3.557 mm |
Pitch | 0.7 mm |
Contacts | 1667 |
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Xeon D-1541 is a 64-bit octa-core x86 microserver SoC introduced by Intel in late 2015. The D-1541 is based on the Broadwell microarchitecture and is fabricated on their 14 nm process. It operates at 2.1 GHz with a TDP of 45 W and a turbo frequency of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.
Cache
- Main article: Broadwell § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics
This SoC has no integrated graphics processing unit.
Memory controller
Integrated Memory Controller | |
Type | DDR3L-1333, DDR3L-1600, DDR4-1600, DDR4-1867, DDR4-2133 |
Controllers | 1 |
Channels | 2 |
ECC Support | Yes |
Max memory | 128 GiB |
Expansions
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Expansion Options
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Networking
Networking | |
SFI interface | Yes |
KR interface | Yes |
KR4 interface | No |
KX interface | Yes |
KX4 interface | No |
10Base-T | No |
100Base-T | No |
1000Base-T | Yes |
10GBase-T | Yes |
Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Xeon D-1541 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon D-1541 - Intel#io + |
back image | ![]() |
base frequency | 2,100 MHz (2.1 GHz, 2,100,000 kHz) + |
bus type | DMI 2.0 + |
clock multiplier | 21 + |
core count | 8 + |
core family | 6 + |
core model | 6 + |
core name | Broadwell DE + |
core stepping | V2 + |
designer | Intel + |
die area | 246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) + |
family | Xeon D + |
first announced | November 1, 2015 + |
first launched | November 1, 2015 + |
full page name | intel/xeon d/d-1541 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has locked clock multiplier | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |
ldate | November 1, 2015 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Server + |
max cpu count | 1 + |
max memory | 131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) + |
max operating temperature | 108 °C + |
max pcie lanes | 8 + |
microarchitecture | Broadwell + |
min operating temperature | 0 °C + |
model number | D-1541 + |
name | Xeon D-1541 + |
package | FCBGA-1667 + |
part number | GG8067402568700 + |
platform | Grangeville + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 581.00 (€ 522.90, £ 470.61, ¥ 60,034.73) + |
release price (tray) | $ 581.00 (€ 522.90, £ 470.61, ¥ 60,034.73) + |
s-spec | SR2DE + |
s-spec (qs) | QJPW + |
series | D-1500 + |
smp max ways | 1 + |
tdp | 45 W (45,000 mW, 0.0603 hp, 0.045 kW) + |
technology | CMOS + |
thread count | 16 + |
transistor count | 3,200,000,000 + |
turbo frequency (1 core) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |