From WikiChip
Difference between revisions of "intel/xeon gold/6252"
< intel‎ | xeon gold

Line 1: Line 1:
 
{{intel title|Xeon Gold 6252}}
 
{{intel title|Xeon Gold 6252}}
−
{{chip
+
{{chip}}
−
|future=Yes
+
'''Xeon Gold 6252''' is a {{arch|64}} [[24-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6252 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 150 W and features a {{intel|turbo boost}} frequency of up to 3.7 GHz.
−
|name=Xeon Gold 6252
 
−
|image=skylake sp (basic).png
 
−
|designer=Intel
 
−
|manufacturer=Intel
 
−
|model number=6252
 
−
|market=Server
 
−
|first announced=March, 2019
 
−
|first launched=March, 2019
 
−
|family=Xeon Gold
 
−
|series=6000
 
−
|locked=Yes
 
−
|frequency=2,100 MHz
 
−
|turbo frequency1=3,700 MHz
 
−
|clock multiplier=21
 
−
|cpuid=0x50655
 
−
|isa=x86-64
 
−
|isa family=x86
 
−
|microarch=Cascade Lake
 
−
|platform=Purley
 
−
|chipset=Lewisburg
 
−
|core name=Cascade Lake SP
 
−
|core family=6
 
−
|process=14 nm
 
−
|technology=CMOS
 
−
|word size=64 bit
 
−
|core count=24
 
−
|thread count=48
 
−
|max cpus=4
 
−
|package module 1={{packages/intel/fclga-3647}}
 
−
}}
 
−
'''Xeon Gold 6252''' is a {{arch|64}} [[24-core]] [[x86]] multi-socket high performance server microprocessor expected to be introduced by [[Intel]] in early 2019. This chip supports up to 4-way multiprocessing. The Gold 6252, which is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm++ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of ? W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up ? GiB of hexa-channel DDR4-2666 memory.
 
−
 
 
−
 
 
−
{{unknown features}}
 
−
 
 
−
 
 
−
 
 
−
== Cache ==
 
−
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
 
−
{{cache size
 
−
|l1 cache=1.5 MiB
 
−
|l1i cache=768 KiB
 
−
|l1i break=24x32 KiB
 
−
|l1i desc=8-way set associative
 
−
|l1d cache=768 KiB
 
−
|l1d break=24x32 KiB
 
−
|l1d desc=8-way set associative
 
−
|l1d policy=write-back
 
−
|l2 cache=24 MiB
 
−
|l2 break=24x1 MiB
 
−
|l2 desc=16-way set associative
 
−
|l2 policy=write-back
 
−
|l3 cache=33 MiB
 
−
|l3 break=24x1.375 MiB
 
−
|l3 desc=11-way set associative
 
−
|l3 policy=write-back
 
−
}}
 
−
 
 
−
== Memory controller ==
 
−
{{memory controller
 
−
|type=DDR4-2666
 
−
|ecc=Yes
 
−
|max mem=? GiB
 
−
|controllers=2
 
−
|channels=6
 
−
|max bandwidth=119.21 GiB/s
 
−
|bandwidth schan=19.87 GiB/s
 
−
|bandwidth dchan=39.74 GiB/s
 
−
|bandwidth qchan=79.47 GiB/s
 
−
|bandwidth hchan=119.21 GiB/s
 
−
}}
 
−
 
 
−
== Expansions ==
 
−
{{expansions
 
−
| pcie revision      = 3.0
 
−
| pcie lanes        = 48
 
−
| pcie config        = x16
 
−
| pcie config 2      = x8
 
−
| pcie config 3      = x4
 
−
}}
 
−
 
 
−
== Features ==
 
−
{{x86 features
 
−
|real=Yes
 
−
|protected=Yes
 
−
|smm=Yes
 
−
|fpu=Yes
 
−
|x8616=Yes
 
−
|x8632=Yes
 
−
|x8664=Yes
 
−
|nx=Yes
 
−
|mmx=Yes
 
−
|emmx=Yes
 
−
|sse=Yes
 
−
|sse2=Yes
 
−
|sse3=Yes
 
−
|ssse3=Yes
 
−
|sse41=Yes
 
−
|sse42=Yes
 
−
|sse4a=No
 
−
|avx=Yes
 
−
|avx2=Yes
 
−
|avx512f=Yes
 
−
|avx512cd=Yes
 
−
|avx512er=No
 
−
|avx512pf=No
 
−
|avx512bw=Yes
 
−
|avx512dq=Yes
 
−
|avx512vl=Yes
 
−
|avx512ifma=No
 
−
|avx512vbmi=No
 
−
|avx5124fmaps=No
 
−
|avx512vnni=Yes
 
−
|avx5124vnniw=No
 
−
|avx512vpopcntdq=No
 
−
|abm=Yes
 
−
|tbm=No
 
−
|bmi1=Yes
 
−
|bmi2=Yes
 
−
|fma3=Yes
 
−
|fma4=No
 
−
|aes=Yes
 
−
|rdrand=Yes
 
−
|sha=No
 
−
|xop=No
 
−
|adx=Yes
 
−
|clmul=Yes
 
−
|f16c=Yes
 
−
|bfloat16=No
 
−
|tbt1=No
 
−
|tbt2=Yes
 
−
|tbmt3=No
 
−
|bpt=No
 
−
|eist=Yes
 
−
|sst=Yes
 
−
|flex=No
 
−
|fastmem=No
 
−
|ivmd=Yes
 
−
|intelnodecontroller=Yes
 
−
|intelnode=Yes
 
−
|kpt=Yes
 
−
|ptt=Yes
 
−
|intelrunsure=Yes
 
−
|mbe=Yes
 
−
|isrt=No
 
−
|sba=No
 
−
|mwt=No
 
−
|sipp=No
 
−
|att=No
 
−
|ipt=No
 
−
|tsx=Yes
 
−
|txt=Yes
 
−
|ht=Yes
 
−
|vpro=Yes
 
−
|vtx=Yes
 
−
|vtd=Yes
 
−
|ept=Yes
 
−
|mpx=No
 
−
|sgx=No
 
−
|securekey=No
 
−
|osguard=No
 
−
|intqat=No
 
−
|dlboost=Yes
 
−
|3dnow=No
 
−
|e3dnow=No
 
−
|smartmp=No
 
−
|powernow=No
 
−
|amdvi=No
 
−
|amdv=No
 
−
|amdsme=No
 
−
|amdtsme=No
 
−
|amdsev=No
 
−
|rvi=No
 
−
|smt=No
 
−
|sensemi=No
 
−
|xfr=No
 
−
|xfr2=No
 
−
|mxfr=No
 
−
|amdpb=No
 
−
|amdpb2=No
 
−
|amdpbod=No
 
−
}}
 

Revision as of 20:47, 7 May 2019

Edit Values
no photo (ic).svg
General Info
Microarchitecture

Xeon Gold 6252 is a 64-bit 24-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6252 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 150 W and features a turbo boost frequency of up to 3.7 GHz.

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/6252&oldid=89958"
Facts about "Xeon Gold 6252 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 6252 - Intel#pcie +
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier21 +
core count24 +
core family6 +
core model85 +
core nameCascade Lake SP +
core steppingB0 +
designerIntel +
familyXeon Gold +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon gold/6252 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Deep Learning Boost +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel VT-d +, Intel VT-x +, Intel vPro Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has intel deep learning boosttrue +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description8-way set associative +
l1d$ size768 KiB (786,432 B, 0.75 MiB) +
l1i$ description8-way set associative +
l1i$ size768 KiB (786,432 B, 0.75 MiB) +
l2$ description16-way set associative +
l2$ size24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) +
l3$ description11-way set associative +
l3$ size35.75 MiB (36,608 KiB, 37,486,592 B, 0.0349 GiB) +
ldateApril 2, 2019 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max case temperature359.15 K (86 °C, 186.8 °F, 646.47 °R) +
max cpu count4 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) +
max memory channels6 +
microarchitectureCascade Lake +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number6252 +
nameXeon Gold 6252 +
packageFCLGA-3647 +
part numberBX806956252 + and CD8069504194401 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 3,655.00 (€ 3,289.50, £ 2,960.55, ¥ 377,671.15) + and $ 3,662.00 (€ 3,295.80, £ 2,966.22, ¥ 378,394.46) +
release price (box)$ 3,662.00 (€ 3,295.80, £ 2,966.22, ¥ 378,394.46) +
release price (tray)$ 3,655.00 (€ 3,289.50, £ 2,960.55, ¥ 377,671.15) +
s-specSRF91 +
s-spec (qs)QRAL +
series6200 +
smp interconnectUPI +
smp interconnect links3 +
smp interconnect rate10.4 GT/s +
smp max ways4 +
socketLGA-3647 + and Socket P +
supported memory typeDDR4-2933 +
tdp150 W (150,000 mW, 0.201 hp, 0.15 kW) +
technologyCMOS +
thread count48 +
turbo frequency (1 core)3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +