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Difference between revisions of "phytium/feiteng/ft-2000+-64"
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'''FT-2000+/64''' is a [[64 core]] [[ARM]] server SoC designed by [[Phytium]] and introduced in [[2019]]. Fabricated on [[TSMC]]'s [[16 nm process]], the chip operates at up 2.3 GHz with a TDP of 96 W. This chip is designed for server, communication, and infrastructure applications. | '''FT-2000+/64''' is a [[64 core]] [[ARM]] server SoC designed by [[Phytium]] and introduced in [[2019]]. Fabricated on [[TSMC]]'s [[16 nm process]], the chip operates at up 2.3 GHz with a TDP of 96 W. This chip is designed for server, communication, and infrastructure applications. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|phytium/microarchitectures/mars_ii#Memory_Hierarchy|l1=Mars II § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=4 MiB | ||
+ | |l1i cache=2 MiB | ||
+ | |l1i break=64x32 KiB | ||
+ | |l1d cache=2 MiB | ||
+ | |l1d break=64x32 KiB | ||
+ | |l2 cache=32 MiB | ||
+ | |l2 break=8x4 MiB | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2400 | ||
+ | |ecc=Yes | ||
+ | |controllers=8 | ||
+ | |channels=8 | ||
+ | |max bandwidth=143.1 GiB/s | ||
+ | |bandwidth schan=17.88 GiB/s | ||
+ | |bandwidth dchan=35.76 GiB/s | ||
+ | |bandwidth qchan=71.53 GiB/s | ||
+ | |bandwidth ochan=143.1 GiB/s | ||
+ | |bandwidth hchan=107.3 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 33 | ||
+ | | pcie config = 4x8+x1 | ||
+ | | pcie config 2 = | ||
+ | | sata revision = | ||
+ | | sata ports = | ||
+ | | usb revision = | ||
+ | | usb revision 2 = | ||
+ | | usb ports = | ||
+ | | usb rate = | ||
+ | | uart = | ||
+ | | uart ports = | ||
+ | | gp io = | ||
+ | }} | ||
+ | |||
+ | == Die == | ||
+ | {{main|phytium/microarchitectures/mars_ii#Die|l1=Mars II § Die}} | ||
+ | :[[File:mars ii die.png|400px]] | ||
+ | |||
+ | |||
+ | :[[File:mars ii die (annotated).png|400px]] |
Revision as of 01:38, 19 February 2019
Edit Values | |
FT-2000+/64 | |
General Info | |
Designer | Phytium |
Manufacturer | TSMC |
Model Number | FT-2000+/64 |
Market | Server |
Introduction | 2019 (announced) 2019 (launched) |
General Specs | |
Family | FT-2000 |
Frequency | 2,3000 MHz |
Microarchitecture | |
ISA | ARMv8.0 (ARM) |
Microarchitecture | Mars II |
Core Name | FTC-662 |
Process | 16 nm |
Transistors | 6,000,000,000 |
Technology | CMOS |
Die | 370 mm² |
Word Size | 64 bit |
Electrical | |
TDP | 96 W |
Packaging | |
Package | FCBGA-3576 (BGA) |
Dimension | 61 mm × 61 mm |
Contacts | 3576 |
Succession | |
FT-2000+/64 is a 64 core ARM server SoC designed by Phytium and introduced in 2019. Fabricated on TSMC's 16 nm process, the chip operates at up 2.3 GHz with a TDP of 96 W. This chip is designed for server, communication, and infrastructure applications.
Contents
Cache
- Main article: Mars II § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Die
- Main article: Mars II § Die
Facts about "FT-2000+/64 - Phytium"
full page name | phytium/feiteng/ft-2000+-64 + |
instance of | microprocessor + |
ldate | 1900 + |