Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/microarchitectures/tiger lake"
| Line 5: | Line 5: | ||
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
| − | |introduction= | + | |introduction=2021 |
|process=10 nm | |process=10 nm | ||
|isa=x86-64 | |isa=x86-64 | ||
Revision as of 17:54, 3 February 2019
| Edit Values | |
| Tiger Lake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2021 |
| Process | 10 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
| Contemporary | |
| Sapphire Rapids | |
Tiger Lake (TGL) is Intel's successor to Ice Lake, a 10nm microarchitecture for mainstream workstations, desktops, and mobile devices.
Process Technology
- Main article: Cannon Lake § Process Technology
Tiger Lake is expected to be manufactured on Intel's third generation enhanced 10nm++ process.
Architecture
Not much is known about Tiger Lake's architecture.
Key changes from Ice Lake
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Facts about "Tiger Lake - Microarchitectures - Intel"
| codename | Tiger Lake + |
| core count | 2 +, 4 +, 6 + and 8 + |
| designer | Intel + |
| first launched | September 2, 2020 + |
| full page name | intel/microarchitectures/tiger lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tiger Lake + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |