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Difference between revisions of "amd/a6/a6-9220c"
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'''A6-9920C''' is a {{arch|64}} [[dual-core]] ultra-low power [[x86]] mobile microprocessor introduced by [[AMD]] in early [[2019]]. This processor is based on AMD's {{amd|Excavator|Excavator microarchitecture|l=arch}} and is fabricated on a [[28 nm process]]. The A6-9920C operates at a base frequency of 1.8 GHz with a [[TDP]] of 6 W and a {{amd|Turbo Core|turbo}} frequency of 2.7 GHz. This APU supports single-channel DDR4-1866 memory and incorporates {{amd|Radeon R5 series}} graphics operating at up to 720 MHz. | '''A6-9920C''' is a {{arch|64}} [[dual-core]] ultra-low power [[x86]] mobile microprocessor introduced by [[AMD]] in early [[2019]]. This processor is based on AMD's {{amd|Excavator|Excavator microarchitecture|l=arch}} and is fabricated on a [[28 nm process]]. The A6-9920C operates at a base frequency of 1.8 GHz with a [[TDP]] of 6 W and a {{amd|Turbo Core|turbo}} frequency of 2.7 GHz. This APU supports single-channel DDR4-1866 memory and incorporates {{amd|Radeon R5 series}} graphics operating at up to 720 MHz. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|amd/microarchitectures/excavator#Memory_Hierarchy|l1=Excavator § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=160 KiB | ||
+ | |l1i cache=96 KiB | ||
+ | |l1i break=1x96 KiB | ||
+ | |l1d cache=64 KiB | ||
+ | |l1d break=2x32 KiB | ||
+ | |l2 cache=1 MiB | ||
+ | |l2 break=2x1 MiB | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-1866 | ||
+ | |ecc=No | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |max bandwidth=13.91 GiB/s | ||
+ | |bandwidth schan=13.91 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=8 | ||
+ | |pcie config=1x8 | ||
+ | }} | ||
+ | }} |
Revision as of 17:51, 7 January 2019
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General Info | |
Microarchitecture |
A6-9920C is a 64-bit dual-core ultra-low power x86 mobile microprocessor introduced by AMD in early 2019. This processor is based on AMD's Excavator microarchitecture and is fabricated on a 28 nm process. The A6-9920C operates at a base frequency of 1.8 GHz with a TDP of 6 W and a turbo frequency of 2.7 GHz. This APU supports single-channel DDR4-1866 memory and incorporates Radeon R5 series graphics operating at up to 720 MHz.
Cache
- Main article: Excavator § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options |
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Facts about "A6-9220C - AMD"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | A6-9220C - AMD#pcie + |
full page name | amd/a6/a6-9220c + |
has ecc memory support | false + |
instance of | microprocessor + |
l1$ size | 160 KiB (163,840 B, 0.156 MiB) + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ size | 96 KiB (98,304 B, 0.0938 MiB) + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
ldate | 1900 + |
max memory bandwidth | 13.91 GiB/s (14,243.84 MiB/s, 14.936 GB/s, 14,935.749 MB/s, 0.0136 TiB/s, 0.0149 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR4-1866 + |