From WikiChip
Difference between revisions of "amd/ryzen 3/3200u"
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{{zen with vega hardware accelerated video table|col=1}} | {{zen with vega hardware accelerated video table|col=1}} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=Yes | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=No | ||
+ | |avx512cd=No | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=No | ||
+ | |avx512dq=No | ||
+ | |avx512vl=No | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=Yes | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |tbt1=No | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=No | ||
+ | |sst=No | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=No | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=No | ||
+ | |txt=No | ||
+ | |ht=No | ||
+ | |vpro=No | ||
+ | |vtx=No | ||
+ | |vtd=No | ||
+ | |ept=No | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |intqat=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=Yes | ||
+ | |amdv=Yes | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=Yes | ||
+ | |sensemi=Yes | ||
+ | |xfr=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | }} | ||
+ | |||
+ | == Die == | ||
+ | {{further|amd/microarchitectures/zen+#Die|l1=Zen+ § Die}} | ||
+ | * [[14 nm process]] | ||
+ | * 4,940,000,000 transistors | ||
+ | * 209.78 mm² die size | ||
+ | |||
+ | |||
+ | : [[File:raven ridge die.png|650px]] | ||
+ | |||
+ | |||
+ | : [[File:raven ridge die (annotated).png|650px]] |
Revision as of 17:22, 7 January 2019
Edit Values | |
Ryzen 3 3200U | |
General Info | |
Designer | AMD |
Manufacturer | GlobalFoundries |
Model Number | 3200U |
Part Number | YM3200C4T2OFG |
Market | Mobile |
Introduction | January 6, 2019 (announced) January 6, 2019 (launched) |
Shop | Amazon |
General Specs | |
Family | Ryzen 3 |
Series | 3000 |
Frequency | 2,600 MHz |
Turbo Frequency | 3,500 MHz (1 core) |
Bus type | PCIe 3.0 |
Clock multiplier | 26 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen+ |
Core Name | Picasso |
Process | 12 nm |
Transistors | 4,940,000,000 |
Technology | CMOS |
Die | 209.78 mm² |
Word Size | 64 bit |
Cores | 2 |
Threads | 4 |
Max Memory | 64 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 15 W |
OP Temperature | 0° C – 105 °C |
Packaging | |
Unknown package "amd,socket_fp5" |
Ryzen 3 3200U is a 64-bit dual-core entry-level performance x86 mobile microprocessor introduced by AMD in early 2019. This processor is based on AMD's Zen+ microarchitecture and is fabricated on a 12 nm process. The 3200U operates at a base frequency of 2.6 GHz with a TDP of 15 W and a Boost frequency of 3.5 GHz. This APU supports up to 32 GiB of dual-channel DDR4-2400 memory and incorporates Radeon Vega 3 Graphics operating at up to 1.2 GHz.
Cache
- Main article: Zen+ § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
This processor has 12 PCIe lanes, 1x8 typically designated for a GPU and 4 additional lanes for storage (e.g., NVMe).
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Expansion Options |
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Graphics
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Integrated Graphics Information
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[Edit] Zen with Radeon Vega Hardware Accelerated Video Capabilities | |||||
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Codec | Encode | Decode | |||
Max FPS | @1080p | @1440p | @2160p | @1080p 4:2:0 | @2160p 4:2:0 |
MPEG-2 (H.262) | 60 FPS | N/A | |||
VC-1 | |||||
VP9 8bpc | 240 FPS | 60 FPS | |||
VP9 10bpc | |||||
MPEG-4 AVC (H.264) 8bpc | 120 FPS | 60 FPS | 30 FPS | ||
MPEG-4 AVC (H.264) 10bpc | |||||
HEVC (H.265) 8bpc | 120 FPS | 60 FPS | 30 FPS | ||
HEVC (H.265) 10bpc | |||||
JPEG/MJPEG 8bpc |
Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Die
- Further information: Zen+ § Die
- 14 nm process
- 4,940,000,000 transistors
- 209.78 mm² die size
Facts about "Ryzen 3 3200U - AMD"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Ryzen 3 3200U - AMD#pcie + |
base frequency | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
bus type | PCIe 3.0 + |
clock multiplier | 26 + |
core count | 2 + |
core name | Picasso + |
designer | AMD + |
die area | 209.78 mm² (0.325 in², 2.098 cm², 209,780,000 µm²) + |
family | Ryzen 3 + |
first announced | January 6, 2019 + |
first launched | January 6, 2019 + |
full page name | amd/ryzen 3/3200u + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd sensemi technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
integrated gpu | Radeon Vega 3 + |
integrated gpu designer | AMD + |
integrated gpu execution units | 3 + |
integrated gpu max frequency | 1,200 MHz (1.2 GHz, 1,200,000 KHz) + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
ldate | January 6, 2019 + |
manufacturer | GlobalFoundries + |
market segment | Mobile + |
max cpu count | 1 + |
max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) + |
max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
max memory channels | 2 + |
max operating temperature | 105 °C + |
microarchitecture | Zen+ + |
min operating temperature | 0° C + |
model number | 3200U + |
name | Ryzen 3 3200U + |
part number | YM3200C4T2OFG + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |
series | 3000 + |
smp max ways | 1 + |
supported memory type | DDR4-2400 + |
tdp | 15 W (15,000 mW, 0.0201 hp, 0.015 kW) + |
technology | CMOS + |
thread count | 4 + |
transistor count | 4,940,000,000 + |
turbo frequency (1 core) | 3,500 MHz (3.5 GHz, 3,500,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |