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Difference between revisions of "arm holdings/microarchitectures/cortex-a8"
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(Key changes from {{\\|ARM11}})
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* [[ARMv7]] (from [[ARMv6]])
 
* [[ARMv7]] (from [[ARMv6]])
 
** Support for {{arm|NEON}} (ASIMD)
 
** Support for {{arm|NEON}} (ASIMD)
 +
** {{arm|VFPv3}} (from {{arm|VFPv2}})
 
** {{arm|TrustZone}}
 
** {{arm|TrustZone}}
 
** {{arm|Thumb-2}}
 
** {{arm|Thumb-2}}

Revision as of 00:39, 31 December 2018

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Cortex-A8 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionOctober 5, 2005
Process65 nm, 45 nm
Pipeline
TypeSuperscalar, Pipelined
OoOENo
SpeculativeYes
Stages13
Decode2-way
Instructions
ISAARMv7
ExtensionsNEON, TrustZone, Thumb-2, Jazelle-RCT, VFPv3
Succession

Cortex-A8 (codename Tiger) is the successor to the ARM11, a low-power performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as an IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A8 was designed by the Arm Austin design center.

Compiler support

Compiler Arch-Specific Arch-Favorable
Arm Compiler -mcpu=cortex-a8 -mtune=cortex-a8
GCC -mcpu=cortex-a8 -mtune=cortex-a8
LLVM -mcpu=cortex-a8 -mtune=cortex-a8

One can specify NEON support using the -mfpu=neon option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because NEON is not fully IEEE 754-compliant. It's possible to use -funsafe-math-optimizations to circumvent that behavior.

Architecture

The Cortex-A8 was the first application processor from the Cortex family. It is also Arm's first superscalar, dual-issue microprocessor.

Key changes from ARM11

  • 65 nm process (from 90 nm)
  • ARMv7 (from ARMv6)
  • ARM reported 2.0 DMIPS/MHz (up from 1.2 DMIPS/MHz)
    • Average IPC reported is 0.9 (based on SPECint95, EEMBC, Mediabench, and others)
  • First superscalar design
    • dual-issue (from single-issue)
    • in-order
    • 13-stage pipeline (up from 8 stages)
    • Targets frequency up to 1 GHz
  • First NEON implementation
    • 10-stage pipeline
  • Dedicated private L2 cache

Block Diagram

cortex-a8 block diagram.svg

Memory Hierarchy

  • Cache
    • L1I Cache
    • L1D Cache
    • L2 Cache
      • 0 KiB OR 128 KiB OR 1 MiB (configurable)
      • 8-way set associative
      • 64 B line size
      • Optional Parity and ECC
  • TLB
    • ITLB
      • 32-entry, fully-associative
      • 4 KiB, 64 KiB, 1 MiB, and 16 MiB page sizes
    • DTLB
      • 32-entry, fully-associative
      • 4 KiB, 64 KiB, 1 MiB, and 16 MiB page sizes

Licensees

Arm named the following companies as licensees.

Die

  • 65 nm process
  • Up to 1 GHz
  • 4 mm² (core only, no NEON, L2 cache, and embedded trace)
  • <= 300 mW
codenameCortex-A8 +
designerARM Holdings +
first launchedOctober 5, 2005 +
full page namearm holdings/microarchitectures/cortex-a8 +
instance ofmicroarchitecture +
instruction set architectureARMv7 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A8 +
pipeline stages13 +
process65 nm (0.065 μm, 6.5e-5 mm) + and 45 nm (0.045 μm, 4.5e-5 mm) +