Revision as of 09:24, 9 December 2018

Exynos 9820 is a 64-bit octa-core ARM high performance mobile system on a chip designed by Samsung and introduced in early 2019. The processor is fabricated on Samsung's 8nm LPP (Low Power Plus) FinFET process and features 8 cores in a tri-cluster configuration consisting of 2 Mongoose M4 big cores and 2 Cortex-A75 middle cores and 4 Cortex-A55 little cores. This chip supports up to 11.6 GiB of quad-channel 16-bit LPDDR4X-3600 memory and incorporates a Mali-G76 MP12 GPU. The 9820 incorporates an LTE modem supporting cat 20 download and upload.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main articles: Mongoose M4 § Cache and Cortex-A76 § Cache

For the Mongoose M4 core cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

For the Cortex-A75 cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

For the Cortex-A55 cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4X-3600 Supports ECC No Max Mem 11.6 GiB Frequency 1800 MHz Controllers 4 Channels 4 Width 16 bit

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU Mali-G76 Designer ARM Holdings Execution Units 12 Max Displays 2 Frequency 600 MHz 0.6 GHz 600,000 KHz Output DSI Standards DirectX 12 OpenCL 2 OpenGL ES 3.2 OpenVG 1.1 Vulkan 1.0

All at 4K UHD 150fps.

Wireless

Wireless Communications
Cellular
4G	LTE Advanced UE Cat DL 20 (2000 Mbps) UE Cat UL 20 (316 Mbps)

ISP

• 24MP Rear
• 24MP Front
• 16MP+16MP Dual

Features

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	NEON Advanced SIMD extension CRC32 CRC-32 checksum Extension Crypto Cryptographic Extension FP Floating-point Extension

Utilizing devices

• Samsung Galaxy S10

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