Semiconductor & Computer Engineering
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Difference between revisions of "hisilicon/kunpeng/920-6426"
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|max memory=512 GiB | |max memory=512 GiB | ||
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| − | '''Hi1620''' is a planned [[octatetraconta-core]] {{arch|64}} [[ARM]] server microprocessor set to be introduced by HiSilicon in late-2018. Fabricated by [[TSMC]] on a [[7 nm process]], this chip incorporates | + | '''Hi1620''' is a planned [[octatetraconta-core]] {{arch|64}} [[ARM]] server microprocessor set to be introduced by HiSilicon in late-2018. Fabricated by [[TSMC]] on a [[7 nm process]], this chip incorporates 64 {{armh|Ares|l=arch}} cores operating at up to 3 GHz. The Hi1620 supports up to 1 TiB of octa-channel DDR4-3200 memory. |
{{unknown features}} | {{unknown features}} | ||
| + | |||
== Cache == | == Cache == | ||
| − | {{main|arm holdings/microarchitectures/ | + | {{main|arm holdings/microarchitectures/ares#Memory_Hierarchy|l1=Ares § Cache}} |
{{cache size | {{cache size | ||
| − | |l1 cache= | + | |l1 cache=8 MiB |
| − | |l1i cache= | + | |l1i cache=4 MiB |
| − | |l1i break= | + | |l1i break=64x64 KiB |
| − | + | |l1d cache=4 MiB | |
| − | |l1d cache= | + | |l1d break=64x64 KiB |
| − | |l1d break= | + | |l2 cache=32 MiB |
| − | + | |l2 break=64x512 KiB | |
| − | |l2 cache= | + | |l3 cache=64 MiB |
| − | |l2 break= | + | |l3 break=64x1 MiB |
| − | |||
| − | |l3 cache= | ||
| − | |l3 break= | ||
| − | |||
}} | }} | ||
== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
| − | |type=DDR4- | + | |type=DDR4-3200 |
|ecc=Yes | |ecc=Yes | ||
| − | |max mem= | + | |max mem=1 TiB |
|controllers=1 | |controllers=1 | ||
| − | |channels= | + | |channels=8 |
|width=64 bit | |width=64 bit | ||
| − | |max bandwidth= | + | |max bandwidth=190.7 GiB/s |
| − | |bandwidth schan= | + | |bandwidth schan=23.84 GiB/s |
| − | |bandwidth dchan= | + | |bandwidth dchan=47.68 GiB/s |
| − | |bandwidth qchan= | + | |bandwidth qchan=95.37 GiB/s |
| + | |bandwidth ochan=190.7 GiB/s | ||
}} | }} | ||
Revision as of 02:36, 16 December 2018
| Edit Values | |
| Hi1620 | |
| General Info | |
| Designer | HiSilicon, ARM Holdings |
| Manufacturer | TSMC |
| Model Number | Hi1620 |
| Market | Server |
| Introduction | September, 2018 (announced) September, 2018 (launched) |
| General Specs | |
| Family | Hi16xx |
| Frequency | 3,000 MHz |
| Microarchitecture | |
| ISA | ARMv8 (ARM) |
| Microarchitecture | Ares |
| Core Name | Ares |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 48 |
| Threads | 48 |
| Max Memory | 512 GiB |
| Multiprocessing | |
| Max SMP | 2-Way (Multiprocessor) |
Hi1620 is a planned octatetraconta-core 64-bit ARM server microprocessor set to be introduced by HiSilicon in late-2018. Fabricated by TSMC on a 7 nm process, this chip incorporates 64 Ares cores operating at up to 3 GHz. The Hi1620 supports up to 1 TiB of octa-channel DDR4-3200 memory.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Ares § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options |
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Features
[Edit/Modify Supported Features]
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Supported ARM Extensions & Processor Features
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Utilizing devices
- HiSilicon D06
This list is incomplete; you can help by expanding it.
Facts about "Kunpeng 920-6426 - HiSilicon"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Kunpeng 920-6426 - HiSilicon#pcie + |
| base frequency | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
| core count | 48 + |
| core name | Ares + |
| designer | HiSilicon + and ARM Holdings + |
| family | Hi16xx + |
| first announced | September 2018 + |
| first launched | September 2018 + |
| full page name | hisilicon/kunpeng/920-6426 + |
| has ecc memory support | true + |
| instance of | microprocessor + |
| isa | ARMv8 + |
| isa family | ARM + |
| l1$ size | 3,840 KiB (3,932,160 B, 3.75 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 2,304 KiB (2,359,296 B, 2.25 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 48 MiB (49,152 KiB, 50,331,648 B, 0.0469 GiB) + |
| ldate | 3000 + |
| manufacturer | TSMC + |
| market segment | Server + |
| max cpu count | 2 + |
| max memory | 524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) + |
| max memory bandwidth | 71.53 GiB/s (73,246.72 MiB/s, 76.805 GB/s, 76,804.753 MB/s, 0.0699 TiB/s, 0.0768 TB/s) + |
| max memory channels | 4 + |
| microarchitecture | Ares + |
| model number | Hi1620 + |
| name | Hi1620 + |
| smp max ways | 2 + |
| supported memory type | DDR4-2400 + |
| technology | CMOS + |
| thread count | 48 + |
| used by | HiSilicon D06 + |
| word size | 64 bit (8 octets, 16 nibbles) + |