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Difference between revisions of "intel/xeon platinum/8260y"
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|avx512vbmi=No
 
|avx512vbmi=No
 
|avx5124fmaps=No
 
|avx5124fmaps=No
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|avx512vnni=Yes
 
|avx5124vnniw=No
 
|avx5124vnniw=No
 
|avx512vpopcntdq=No
 
|avx512vpopcntdq=No
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|clmul=Yes
 
|clmul=Yes
 
|f16c=Yes
 
|f16c=Yes
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|bfloat16=No
 
|tbt1=No
 
|tbt1=No
 
|tbt2=Yes
 
|tbt2=Yes
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|securekey=No
 
|securekey=No
 
|osguard=No
 
|osguard=No
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|intqat=No
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|dlboost=Yes
 
|3dnow=No
 
|3dnow=No
 
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|e3dnow=No
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|sensemi=No
 
|sensemi=No
 
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Revision as of 00:25, 19 November 2018

Edit Values
Xeon Platinum 8260C
skylake sp (basic).png
General Info
DesignerIntel
ManufacturerIntel
Model Number8260C
MarketServer
IntroductionDecember 2018 (announced)
December 2018 (launched)
ShopAmazon
General Specs
FamilyXeon Platinum
Series8000
Frequency2,400 MHz
Turbo Frequency3,900 MHz (1 core)
Clock multiplier24
CPUID0x50655
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores24
Threads48
Multiprocessing
Max SMP8-Way (Multiprocessor)
Electrical
TDP165 W
Packaging
Template:packages/intel/fclga-3647

Xeon Platinum 8260C is a 64-bit 24-core x86 multi-socket highest performance server microprocessor expected to be introduced by Intel in late 2018. This chip supports up to 8-way multiprocessing. The Platinum 8260C, which is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm++ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.3 GHz with a TDP of 165 W and a turbo boost frequency of up to 3.9 GHz, supports up ? GiB of hexa-channel DDR4-2666 memory.

Cache

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.5 MiB
1,536 KiB
1,572,864 B
L1I$768 KiB
786,432 B
0.75 MiB
24x32 KiB8-way set associative 
L1D$768 KiB
786,432 B
0.75 MiB
24x32 KiB8-way set associativewrite-back
L2$24 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
  24x1 MiB16-way set associativewrite-back
L3$33 MiB
33,792 KiB
34,603,008 B
0.0322 GiB
  24x1.375 MiB11-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem? GiB
Controllers2
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4


Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
Node CtrlrNode Controller Support
DL BoostDeep Learning Boost
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_platinum/8260y&oldid=84201"
Facts about "Xeon Platinum 8260Y - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Platinum 8260Y - Intel#io +
base frequency2,400 MHz (2.4 GHz, 2,400,000 kHz) +
chipsetLewisburg +
clock multiplier24 +
core count24 +
core family6 +
core nameCascade Lake SP +
cpuid0x50655 +
designerIntel +
familyXeon Platinum +
first announcedDecember 2018 +
first launchedDecember 2018 +
full page nameintel/xeon platinum/8260y +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost +
has intel deep learning boosttrue +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description8-way set associative +
l1d$ size768 KiB (786,432 B, 0.75 MiB) +
l1i$ description8-way set associative +
l1i$ size768 KiB (786,432 B, 0.75 MiB) +
l2$ description16-way set associative +
l2$ size24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) +
l3$ description11-way set associative +
l3$ size33 MiB (33,792 KiB, 34,603,008 B, 0.0322 GiB) +
ldateDecember 2018 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer +
max cpu count8 +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureCascade Lake +
model number8260C +
nameXeon Platinum 8260C +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
series8000 +
smp max ways8 +
supported memory typeDDR4-2666 +
tdp165 W (165,000 mW, 0.221 hp, 0.165 kW) +
technologyCMOS +
thread count48 +
turbo frequency (1 core)3,900 MHz (3.9 GHz, 3,900,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +