Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/cores/cascade lake ap"
(→Overview) |
|||
| Line 19: | Line 19: | ||
== Overview == | == Overview == | ||
| − | {{ | + | Cascade Lake AP comprise of multiple {{intel|Cascade Lake|l=arch}} dies in a single package. Those processors support up to 48 cores, 96 threads, and up to 12 DDR4 channels. |
=== Common Features === | === Common Features === | ||
| − | {{ | + | * 12-channel memory |
| + | ** UP to DDR4-2666 MT/s | ||
| + | ** ECC support | ||
| + | * '''TDP:''' ? W to ? W | ||
| + | * '''PCIe:''' x? Lanes of PCIe Gen 3 | ||
| + | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL, AVX512VNNI) | ||
| + | * '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}} | ||
{{clear}} | {{clear}} | ||
Revision as of 03:09, 5 November 2018
| Edit Values | |
| Cascade Lake AP | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Microarchitecture | |
| ISA | x86-64 |
| Microarchitecture | Cascade Lake |
| Word Size | 8 octets 64 bit16 nibbles |
| Process | 14 nm 0.014 μm 1.4e-5 mm |
| Technology | CMOS |
| Packaging | |
| Package | FCBGA-5903 (BGA) |
| Pitch | 0.99 mm |
| Contacts | 5903 |
Cascade Lake AP (Cascade Lake Advanced Performance) is code name for a series of high core-count multi-chip packaged server multiprocessors based on the Cascade Lake microarchitecture.
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Overview
Cascade Lake AP comprise of multiple Cascade Lake dies in a single package. Those processors support up to 48 cores, 96 threads, and up to 12 DDR4 channels.
Common Features
- 12-channel memory
- UP to DDR4-2666 MT/s
- ECC support
- TDP: ? W to ? W
- PCIe: x? Lanes of PCIe Gen 3
- ISA: Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL, AVX512VNNI)
- Features: Speed Shift, vPro, VT-x, TSX, TXT
Cascade Lake AP Processors
 |
This section is empty; you can help add the missing info by editing this page. |
See also
|
|
Facts about "Cascade Lake AP - Cores - Intel"
| designer | Intel + |
| instance of | core + |
| isa | x86-64 + |
| manufacturer | Intel + |
| microarchitecture | Cascade Lake + |
| name | Cascade Lake AP + |
| package | FCBGA-5903 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |