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Difference between revisions of "amd/microarchitectures/zen 2"
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* <code>{{x86|WBNOINVD}}</code> - Force cache line write-back without invalidation | * <code>{{x86|WBNOINVD}}</code> - Force cache line write-back without invalidation | ||
| − | == | + | == Bibliography == |
* AMD 'Tech Day', February 22, 2017 | * AMD 'Tech Day', February 22, 2017 | ||
* AMD 2017 Financial Analyst Day, May 16, 2017 | * AMD 2017 Financial Analyst Day, May 16, 2017 | ||
| + | * AMD GCC 9 znver2 enablement [https://gcc.gnu.org/ml/gcc-patches/2018-10/msg01982.html patch] | ||
== See Also == | == See Also == | ||
* Intel {{intel|Ice Lake|l=arch}} | * Intel {{intel|Ice Lake|l=arch}} | ||
Revision as of 07:02, 31 October 2018
| Edit Values | |
| Zen 2 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | AMD |
| Manufacturer | TSMC |
| Introduction | 2019 |
| Process | 7 nm |
| Succession | |
Zen 2 is a planned microarchitecture being developed by AMD as a successor to Zen+. Zen 2 is expected to be succeeded by Zen 3.
Contents
History
Zen 2 is set to succeed Zen in the future, sometimes around 2019. In February of 2017 Lisa Su, AMD's CEO announced their future roadmap to include Zen 2 and later Zen 3. On Investor's Day May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 2 is set to utilize 7 nm process.
Codenames
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
| Core | C/T | Target |
|---|---|---|
| Rome | ?/? | High-end server multiprocessors |
| Castle Peak | ?/? | workstation & enthusiasts market processors |
| Matisse | ?/? | Mainstream to high-end desktops & enthusiasts market processors |
| Picasso | ?/? | Mainstream desktop & mobile processors with GPU |
Architecture
Nothing is currently known about the architectural improvements that is being done to Zen 2.
Key changes from Zen
- 7 nm process (from 14 nm)
This list is incomplete; you can help by expanding it.
New instructions
Zen 2 introduced a number of new x86 instructions:
-
CLWB- Force cache line write-back without flush -
RDPID- Read Processor ID -
WBNOINVD- Force cache line write-back without invalidation
Bibliography
- AMD 'Tech Day', February 22, 2017
- AMD 2017 Financial Analyst Day, May 16, 2017
- AMD GCC 9 znver2 enablement patch
See Also
- Intel Ice Lake
Facts about "Zen 2 - Microarchitectures - AMD"
| codename | Zen 2 + |
| designer | AMD + |
| first launched | 2019 + |
| full page name | amd/microarchitectures/zen 2 + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Zen 2 + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + |