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Difference between revisions of "nvidia/microarchitectures/carmel"
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* Eight-core cluster
 
* Eight-core cluster
 
** 4x Core duplexes
 
** 4x Core duplexes
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== Overview ==
 
−
Carmel is a CPU microarchitecture designed by Nvidia for their SoCs. The design consists of an 8-core cluster made of 4 core duplexes. The entire complex has [[cache coherency]] as well as an I/O coherent memory subsystem which is designed for communication with the various other accelerators on their SoCs such as the vision accelerator, deep learning accelerator, multimedia engine, and the GPU.
 
  
 
=== Memory Hierarchy ===
 
=== Memory Hierarchy ===
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**** Shared by entire cluster
 
**** Shared by entire cluster
 
**** Exclusive
 
**** Exclusive
 +
 +
== Overview ==
 +
Carmel is a CPU microarchitecture designed by Nvidia for their SoCs. The design consists of an 8-core cluster made of 4 core duplexes. The entire complex has [[cache coherency]] as well as an I/O coherent memory subsystem which is designed for communication with the various other accelerators on their SoCs such as the vision accelerator, deep learning accelerator, multimedia engine, and the GPU.
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 +
== Die ==
 +
=== CPU Complex ===
 +
* 8 cores
 +
** 4 duplexes
 +
** shared L3
 +
* ~62.25 mm² die size area
 +
 +
:[[File:nvidia carmel complex.png|600px]]
 +
 +
 +
:[[File:nvidia carmel complex (annotated).png|600px]]
 +
 +
=== CPU Duplex ===
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* 2 cores
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* ~11.4 mm² die size area
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 +
:[[File:nvidia carmel duplex.png|400px]]
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 +
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:[[File:nvidia carmel duplex (annotated).png|400px]]
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=== Core ===
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* ~5.75 mm² die size area
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:[[File:nvidia carmel core.png|200px]]
  
 
== Bibliography ==
 
== Bibliography ==
 
* IEEE Hot Chips 30 Symposium (HCS) 2018.
 
* IEEE Hot Chips 30 Symposium (HCS) 2018.

Revision as of 13:02, 30 August 2018

Edit Values
Carmel µarch
General Info
Arch TypeCPU
DesignerNvidia
ManufacturerTSMC
IntroductionJanuary 7, 2018
Process12 nm
Core Configs8
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAARMv8
Cache
L2 Cache2 MiB/cluster
L3 Cache4 MiB/complex
Succession

Carmel is a the successor to Denver 2, an ARM microarchitecture for Nvidia's Tegra series of SoCs.

Architecture

Nvidia disclosed very few details regarding Carmel.

  • 12 nm (12FF)
  • ARMv8.2 (Only AArch64)
    • ARM RAS standard support
  • Eight-core cluster
    • 4x Core duplexes

Memory Hierarchy

  • Cache
    • L1
    • L2
      • 2 MiB
        • Shared per duplex
    • L3
      • 4 MiB
        • Shared by entire cluster
        • Exclusive

Overview

Carmel is a CPU microarchitecture designed by Nvidia for their SoCs. The design consists of an 8-core cluster made of 4 core duplexes. The entire complex has cache coherency as well as an I/O coherent memory subsystem which is designed for communication with the various other accelerators on their SoCs such as the vision accelerator, deep learning accelerator, multimedia engine, and the GPU.

Die

CPU Complex

  • 8 cores
    • 4 duplexes
    • shared L3
  • ~62.25 mm² die size area
nvidia carmel complex.png


nvidia carmel complex (annotated).png

CPU Duplex

  • 2 cores
  • ~11.4 mm² die size area
nvidia carmel duplex.png


nvidia carmel duplex (annotated).png

Core

  • ~5.75 mm² die size area
nvidia carmel core.png

Bibliography

  • IEEE Hot Chips 30 Symposium (HCS) 2018.
Retrieved from "https://en.wikichip.org/w/index.php?title=nvidia/microarchitectures/carmel&oldid=82007"
Facts about "Carmel - Microarchitectures - Nvidia"
RDF feed
codenameCarmel +
core count8 +
designerNvidia +
first launchedJanuary 7, 2018 +
full page namenvidia/microarchitectures/carmel +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCarmel +
process12 nm (0.012 μm, 1.2e-5 mm) +