Difference between revisions of "intel/microarchitectures/goldmont plus"

	Edit Values
	Goldmont Plus µarch
	General Info
Arch Type	CPU
Designer	Intel
Manufacturer	Intel
Introduction	December 11, 2017
Process	14 nm
Core Configs	2, 4
	Pipeline
Type	Superscalar
OoOE	Yes
Speculative	Yes
Reg Renaming	Yes
	Instructions
ISA	x86-64
Extensions	MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA
	Cache
L1I Cache	32 KiB/Core; 8-way set associative
L1D Cache	24 KiB/Core; 6-way set associative
L2 Cache	4 MiB/4 Cores; 16-way set associative
	Cores
Core Names	Gemini Lake
	Succession
	Goldmont Tremont

Revision as of 22:08, 29 August 2018

Goldmont Plus (GLM+, GLP) is Intel's 14 nm microarchitecture of system on chips for the ultra-low power (ULP) devices serving as a successor to Goldmont. Goldmont Plus-based processors and SoCs are part of the Atom, Pentium Silver, and Celeron families.

Codenames

Core	Abbrev	Target
Gemini Lake	GLK	Low-power PCs, tablets, and embedded devices

Brands

Intel released Goldmont Plus under 2 main brand families:

Logo	Family	General Description	Differentiating Features
Logo	Family	General Description	Cores	HT	AES	SHA	AVX	TBT	ECC
	Celeron	Entry-level Budget	2-4	✘	✔	✔	✘	✘	✘
	Pentium Silver	Budget	4	✘	✔	✔	✘	✘	✘

Release Dates

Goldmont Plus processors were launched on December 11, 2017 for desktop, mobile and embedded devices. Server-based parts are expected to be introduced in 2018.

Technology

Goldmont Plus, like its predecessor, is manufactured on Intel's original 14 nm process (as opposed to 14nm+ or 14nm++).

Compiler support

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Compiler	Arch-Specific	Arch-Favorable
ICC	`-march=goldmont`	`-mtune=goldmont`
GCC	`-march=goldmont`	`-mtune=goldmont`
LLVM	`-march=goldmont`	`-mtune=goldmont`
Visual Studio	`?`	`?`

CPUID

Core	Extended Family	Family	Extended Model	Model
Gemini Lake	0	6	7	10
Gemini Lake	Family 6 Model 10

Architecture

Despite the name "Goldmont Plus", this microarchitecture is a very large implementational jump from "Goldmont" with improvements across the board from the caches to a wider pipeline.

Key changes from Goldmont

Core
- Front End
  - Enhanced branch prediction
- Back End
  - 4-way allocation (from 3)
  - 4-way retire (from 3)
- Larger reservation station
- Larger ROB
- Execution Units
- Wider integer execution unit
- New dedicated JEU port
  - Supports faster branch redirection.
- Radix-1024 floating point divider for fast scalar/packed single, double and extended precision floating point divides
- Improved AES instruction latency and throughput.
- Memory Subsystem
  - 64 KiB 2nd level pre-decode cache (from 16 KiB)
  - Larger load buffer
  - Larger store buffer
  - Improved store-to-load forwarding latency store data from register
  - New STLB
    - Shared by instruction and data
  - Paging Cache Enhancements (PxE/ePxE caches)
Cache
- 4 MiB L2 per quad core module (Up from 1 MiB per duplex)
Graphics
- Gen 9.5 execution engines, Gen 10 Display
New Integration
- Integrated Connectivity CNVi
  - Supports up to Wireless-AC CRFs
- HDMI 2.0 (from 1.4a)
  - 2160p (4K) @ 60 Hz (from 24 Hz)
- VP9 10-bit Profile2 hardware decoding
- HD Graphics 50x → UHD Graphics 60x
  - HD Graphics 505 → UHD Graphics 605 (Pentium Silver J/N 5xxx with 18EU)
  - HD Graphics 500 → UHD Graphics 600 (Celeron J/N 4xxx with 12EU)

New instructions

Goldmont Plus introduced a number of new instructions:

SGX1 - Software Guard Extensions, Version 1
UMIP - User-mode instruction prevention
PTWRITE - Trace logger write user data
RDPID - Read Processor ID

Block Diagram

This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy

Cache
- Hardware prefetchers
- L1 Cache:
  - 32 KiB 8-way set associative instruction, 64 B line size
  - 24 KiB 6-way set associative data, 64 B line size
  - Per core
- L2 Cache:
  - 2 MiB 16-way set associative, 64 B line size
  - Per 2 cores
- L3 Cache:
  - No level 3 cache
- RAM
  - Maximum of 1 GiB, 2 GiB, 4 GiB, 8 GiB
  - dual 32-bit channels, 1 or 2 ranks per channel

Multithreading

Goldmont Plus, like Goldmont has no support for Intel Hyper-Threading Technology.

New Integration

Integrated Connectivity (CNVi)

Main article: CNVi

A new integration to Goldmont Plus is Integrated Connectivity (CNVi) which is an architecture for wireless connectivity devices. CNVi attempts to simplify vendors bill of material (BOM) size and cost by integrating the majority of the expensive functionality found in an RF chip. The only thing not integrated are the actual analog and RF functions which come from a relatively inexpensive companion RF (CRF) module connected via a standard M.2 card and provides support for things such as IEEE 802.11ac.

All Goldmont Plus Chips

	List of Goldmont Plus-based Processors
	Main processor									GPU
Model	Family	Price	Launched	Cores	L2$	TDP	SDP	Base	Turbo	Name	Base	Turbo
	Desktop
J4005	Celeron	$ 107.00 € 96.30 £ 86.67 ¥ 11,056.31	11 December 2017	2	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	10 W 10,000 mW 0.0134 hp 0.01 kW		2,000 MHz 2 GHz 2,000,000 kHz	2,700 MHz 2.7 GHz 2,700,000 kHz	UHD Graphics 600	250 MHz 0.25 GHz 250,000 KHz	700 MHz 0.7 GHz 700,000 KHz
J4105	Celeron	$ 107.00 € 96.30 £ 86.67 ¥ 11,056.31	11 December 2017	4	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	10 W 10,000 mW 0.0134 hp 0.01 kW		1,500 MHz 1.5 GHz 1,500,000 kHz	2,500 MHz 2.5 GHz 2,500,000 kHz	UHD Graphics 600	250 MHz 0.25 GHz 250,000 KHz	750 MHz 0.75 GHz 750,000 KHz
J5005	Pentium Silver	$ 161.00 € 144.90 £ 130.41 ¥ 16,636.13	11 December 2017	4	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	10 W 10,000 mW 0.0134 hp 0.01 kW		1,500 MHz 1.5 GHz 1,500,000 kHz	2,800 MHz 2.8 GHz 2,800,000 kHz	UHD Graphics 605	250 MHz 0.25 GHz 250,000 KHz	800 MHz 0.8 GHz 800,000 KHz
	Mobile
N4000	Celeron	$ 107.00 € 96.30 £ 86.67 ¥ 11,056.31	11 December 2017	2	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	6 W 6,000 mW 0.00805 hp 0.006 kW	4.8 W 4,800 mW 0.00644 hp 0.0048 kW	1,100 MHz 1.1 GHz 1,100,000 kHz	2,600 MHz 2.6 GHz 2,600,000 kHz	UHD Graphics 600	200 MHz 0.2 GHz 200,000 KHz	650 MHz 0.65 GHz 650,000 KHz
N4100	Celeron	$ 107.00 € 96.30 £ 86.67 ¥ 11,056.31	11 December 2017	4	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	6 W 6,000 mW 0.00805 hp 0.006 kW	4.8 W 4,800 mW 0.00644 hp 0.0048 kW	1,100 MHz 1.1 GHz 1,100,000 kHz	2,400 MHz 2.4 GHz 2,400,000 kHz	UHD Graphics 600	200 MHz 0.2 GHz 200,000 KHz	700 MHz 0.7 GHz 700,000 KHz
N5000	Pentium Silver	$ 161.00 € 144.90 £ 130.41 ¥ 16,636.13	11 December 2017	4	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	6 W 6,000 mW 0.00805 hp 0.006 kW	4.8 W 4,800 mW 0.00644 hp 0.0048 kW	1,100 MHz 1.1 GHz 1,100,000 kHz	2,700 MHz 2.7 GHz 2,700,000 kHz	UHD Graphics 605	200 MHz 0.2 GHz 200,000 KHz	750 MHz 0.75 GHz 750,000 KHz
Count: 6

@@ Line 98: / Line 98: @@
 == Architecture ==
 Despite the name "Goldmont Plus", this microarchitecture is a very large implementational jump from "Goldmont" with improvements across the board from the caches to a wider pipeline.
-[https://hexus.net/media/uploaded/2017/12/974132cc-e2a7-4e0d-abcc-4738a7de767d.jpg arhitecture]
 === Key changes from {{\\|Goldmont}} ===
 * Core

codename	Goldmont Plus +
core count	2 + and 4 +
designer	Intel +
first launched	December 11, 2017 +
full page name	intel/microarchitectures/goldmont plus +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Goldmont Plus +
process	14 nm (0.014 μm, 1.4e-5 mm) +

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