Difference between revisions of "amd/ryzen threadripper/2950x"

	Edit Values
	Ryzen Threadripper 2950X
	General Info
Designer	AMD
Manufacturer	GlobalFoundries
Model Number	2950X
Market	Desktop
Introduction	August, 2018 (announced); August, 2018 (launched)
Shop	Amazon
	General Specs
Family	Ryzen Threadripper
Series	Ryzen
Locked	No
Frequency	3,500 MHz
Turbo Frequency	4,400 MHz (1 core)
Bus rate	4 × 8 GT/s
Clock multiplier	35
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Zen+
Core Family	23
Process	12 nm
Technology	CMOS
Die	213 mm²
MCP	Yes (2 dies)
Word Size	64 bit
Cores	16
Threads	32
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Electrical
TDP	180 W

Revision as of 16:12, 3 August 2018

Ryzen Threadripper 2950X is a 64-bit hexadeca-core high-performance x86 desktop microprocessor introduced by AMD in mid-2018. The 2950X, which is based on their Zen+ microarchitecture, is fabricated on a 12 nm process. The 2950X operates at a base frequency of 3.5 GHz with a TDP of 180 W and a boost of up to 4.4 GHz

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Leaked Info! Some of the information presented in this article is solely based on leaks that were published online or obtained directly by WikiChip. It goes without saying that this information could change, be incomplete, wrong, or even made up. It's highly advised to wait for an official product announcement.

Cache

Main article: Zen+ § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

1.5 MiB

1,536 KiB
1,572,864 B

L1I$	1 MiB 1,024 KiB 1,048,576 B	16x64 KiB	4-way set associative
L1D$	512 KiB 524,288 B 0.5 MiB	16x32 KiB	8-way set associative	write-back

L2$

8 MiB

8,192 KiB
8,388,608 B
0.00781 GiB

		16x512 KiB	8-way set associative	write-back

L3$

32 MiB

32,768 KiB
33,554,432 B
0.0313 GiB

		4x8 MiB	16-way set associative

@@ Line 26: / Line 26: @@
 |die area=213 mm²
 |mcp=Yes
-|die count=4
+|die count=2
 |word size=64 bit
 |core count=16

base frequency	3,500 MHz (3.5 GHz, 3,500,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
clock multiplier	35 +
core count	16 +
core family	23 +
designer	AMD +
die area	213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) +
die count	2 +
family	Ryzen Threadripper +
first announced	August 2018 +
first launched	August 2018 +
full page name	amd/ryzen threadripper/2950x +
has locked clock multiplier	false +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description	8-way set associative +
l1d$ size	512 KiB (524,288 B, 0.5 MiB) +
l1i$ description	4-way set associative +
l1i$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l2$ description	8-way set associative +
l2$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description	16-way set associative +
l3$ size	32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldate	3000 +
manufacturer	GlobalFoundries +
market segment	Desktop +
max cpu count	1 +
microarchitecture	Zen+ +
model number	2950X +
name	Ryzen Threadripper 2950X +
process	12 nm (0.012 μm, 1.2e-5 mm) +
series	Ryzen +
smp max ways	1 +
tdp	180 W (180,000 mW, 0.241 hp, 0.18 kW) +
technology	CMOS +
thread count	32 +
turbo frequency (1 core)	4,400 MHz (4.4 GHz, 4,400,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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Revision as of 16:12, 3 August 2018

Cache