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Difference between revisions of "hisilicon/kunpeng/hi1616"
< hisilicon‎ | kunpeng

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|thread count=32
 
|thread count=32
 
|max cpus=2
 
|max cpus=2
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|max memory=256 GiB
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|max memory=512 GiB
 
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}}
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'''Hi1616''' is a [[dotriaconta-core]] {{arch|64}} [[ARM]] server microprocessor introduced by HiSilicon in mid-2017. Fabricated by [[TSMC]] on a [[16 nm process]], this chip incorporates 32 {{armh|Cortex-A72}} cores operating at 2.4 GHz. The Hi1616 supports up to 256 GiB of quad-channel DDR4-2400 memory.
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'''Hi1616''' is a [[dotriaconta-core]] {{arch|64}} [[ARM]] server microprocessor introduced by HiSilicon in mid-2017. Fabricated by [[TSMC]] on a [[16 nm process]], this chip incorporates 32 {{armh|Cortex-A72}} cores operating at 2.4 GHz. The Hi1616 supports up to 512 GiB of quad-channel DDR4-2400 memory.
  
 
== Cache ==
 
== Cache ==
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|type=DDR4-2400
 
|type=DDR4-2400
 
|ecc=Yes
 
|ecc=Yes
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|max mem=256 GiB
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|max mem=512 GiB
 
|controllers=1
 
|controllers=1
 
|channels=4
 
|channels=4

Revision as of 00:55, 1 August 2018

Edit Values
Hi1616
General Info
DesignerHiSilicon,
ARM Holdings
ManufacturerTSMC
Model NumberHi1616
MarketServer
IntroductionAugust, 2017 (announced)
August, 2017 (launched)
General Specs
FamilyHi16xx
Frequency2,400 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A72
Core NameCortex-A72
Process16 nm
TechnologyCMOS
Word Size64 bit
Cores32
Threads32
Max Memory512 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)

Hi1616 is a dotriaconta-core 64-bit ARM server microprocessor introduced by HiSilicon in mid-2017. Fabricated by TSMC on a 16 nm process, this chip incorporates 32 Cortex-A72 cores operating at 2.4 GHz. The Hi1616 supports up to 512 GiB of quad-channel DDR4-2400 memory.

Cache

Main article: Cortex-A57 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$2.5 MiB
2,560 KiB
2,621,440 B
L1I$1.5 MiB
1,536 KiB
1,572,864 B
32x48 KiB8-way set associative 
L1D$1 KiB
1,024 B
9.765625e-4 MiB
32x32 KiB8-way set associative 
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  32x256 KiB8-way set associative 
L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  32x1 MiB16-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem512 GiB
Controllers1
Channels4
Width64 bit
Max Bandwidth71.53 GiB/s
73,246.72 MiB/s
76.805 GB/s
76,804.753 MB/s
0.0699 TiB/s
0.0768 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 16
Configuration: 2x8

Utilizing devices

  • HiSilicon D05

This list is incomplete; you can help by expanding it.

Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/kunpeng/hi1616&oldid=80895"
Facts about "Kunpeng 916 (Hi1616) - HiSilicon"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Kunpeng 916 (Hi1616) - HiSilicon#pcie +
base frequency2,400 MHz (2.4 GHz, 2,400,000 kHz) +
core count32 +
core nameCortex-A72 +
designerHiSilicon + and ARM Holdings +
familyHi16xx +
first announcedAugust 2017 +
first launchedAugust 2017 +
full page namehisilicon/kunpeng/hi1616 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size2,560 KiB (2,621,440 B, 2.5 MiB) +
l1d$ description8-way set associative +
l1d$ size1 KiB (1,024 B, 9.765625e-4 MiB) +
l1i$ description8-way set associative +
l1i$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l2$ description8-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description16-way set associative +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldateAugust 2017 +
manufacturerTSMC +
market segmentServer +
max cpu count2 +
max memory524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
max memory bandwidth71.53 GiB/s (73,246.72 MiB/s, 76.805 GB/s, 76,804.753 MB/s, 0.0699 TiB/s, 0.0768 TB/s) +
max memory channels4 +
microarchitectureCortex-A72 +
model numberHi1616 +
nameHi1616 +
process16 nm (0.016 μm, 1.6e-5 mm) +
smp max ways2 +
supported memory typeDDR4-2400 +
technologyCMOS +
thread count32 +
used byHiSilicon D05 +
word size64 bit (8 octets, 16 nibbles) +