From WikiChip
Difference between revisions of "hisilicon/kunpeng/hi1612"
< hisilicon‎ | kunpeng

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|thread count=32
 
|thread count=32
 
|max cpus=1
 
|max cpus=1
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}}
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 +
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== Cache ==
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{{main|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A57 § Cache}}
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{{cache size
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|l1 cache=2.5 MiB
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|l1i cache=1.5 MiB
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|l1i break=32x48 KiB
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|l1i desc=8-way set associative
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|l1d cache=1 KiB
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|l1d break=32x32 KiB
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|l1d desc=8-way set associative
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|l2 cache=8 MiB
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|l2 break=32x256 KiB
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|l2 desc=8-way set associative
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|l3 cache=32 MiB
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|l3 break=32x1 MiB
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|l3 desc=16-way set associative
 
}}
 
}}

Revision as of 23:14, 31 July 2018

Edit Values
Hi1612
General Info
DesignerHiSilicon,
ARM Holdings
ManufacturerTSMC
Model NumberHi1610
MarketServer
General Specs
FamilyHi16xx
Frequency2,100 MHz
Microarchitecture
ISAARMv8 (ARM)
TechnologyCMOS
Word Size64 bit
Cores32
Threads32
Multiprocessing
Max SMP1-Way (Uniprocessor)


Cache

Main article: Cortex-A57 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$2.5 MiB
2,560 KiB
2,621,440 B
L1I$1.5 MiB
1,536 KiB
1,572,864 B
32x48 KiB8-way set associative 
L1D$1 KiB
1,024 B
9.765625e-4 MiB
32x32 KiB8-way set associative 
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  32x256 KiB8-way set associative 
L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  32x1 MiB16-way set associative 
Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/kunpeng/hi1612&oldid=80875"
Facts about "Hi1612 - HiSilicon"
RDF feed
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
core count32 +
designerHiSilicon + and ARM Holdings +
familyHi16xx +
full page namehisilicon/kunpeng/hi1612 +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size2,560 KiB (2,621,440 B, 2.5 MiB) +
l1d$ description8-way set associative +
l1d$ size1 KiB (1,024 B, 9.765625e-4 MiB) +
l1i$ description8-way set associative +
l1i$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l2$ description8-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description16-way set associative +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldate1900 +
manufacturerTSMC +
market segmentServer +
max cpu count1 +
model numberHi1610 +
nameHi1612 +
smp max ways1 +
technologyCMOS +
thread count32 +
word size64 bit (8 octets, 16 nibbles) +