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Difference between revisions of "cavium/thunderx2/cn9965"
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Latest revision as of 22:14, 3 December 2018

Edit Values
ThunderX2 CN9965
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN9965
Part NumberCN9965-2500LG4077-Y21-G,
CN9965-2400LG4077-Y21-G,
CN9965-2300LG4077-Y21-G,
CN9965-2200LG4077-Y21-G,
CN9965-2100LG4077-Y21-G,
CN9965-2000LG4077-Y21-G,
CN9965-1800LG4077-Y21-G
MarketServer
IntroductionMay 7, 2018 (announced)
May 7, 2018 (launched)
General Specs
FamilyThunderX2
Frequency1,800 MHz, 2,000 MHz, 2,100 MHz, 2,200 MHz, 2,300 MHz, 2,400 MHz, 2,500 MHz
Microarchitecture
ISAARMv8.1 (ARM)
MicroarchitectureVulcan
Process16 nm
TechnologyCMOS
Word Size64 bit
Cores20
Threads40
Max Memory2 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Packaging
PackageFCLGA-4077 (LGA)
Contacts4077

ThunderX2 CN9965 is a 64-bit icosa-core high-performance ARM server microprocessor introduced by Cavium in mid-2018. The microprocessor, which is based on the Vulcan microarchitecture, is fabricated on TSMC's 16 nm process. Depending on the exact SKU, the CN9965 operates between 1.8 GHz and 2.5 GHz and supports up to quad-/hexa-channel DDR4-2666 memory.

Cache[edit]

Main article: Vulcan § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.25 MiB
1,280 KiB
1,310,720 B
L1I$640 KiB
655,360 B
0.625 MiB
20x32 KiB8-way set associative 
L1D$640 KiB
655,360 B
0.625 MiB
20x32 KiB8-way set associative 
L2$5 MiB
5,120 KiB
5,242,880 B
0.00488 GiB
  20x256 KiB8-way set associative 
L3$20 MiB
20,480 KiB
20,971,520 B
0.0195 GiB
  20x1 MiB  

Memory controller[edit]

The 1.8 GHz model only supports quad-channel memory while all other models support hexa-channel memory.

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem2 TiB
Controllers2
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 56
Configuration: x16, x8, x4, x1
SATARevision: 3
Max Ports: 2
USBRevision: 3
Max Ports: 2


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
TrustZoneTrustZone Security Extensions
PMUv3ARMv8 PMUv3 Performance Monitors Extension
CRC32CRC-32 checksum Extension
CryptoCryptographic Extension
FPFloating-point Extension
SIMDAdvanced SIMD extension
Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/thunderx2/cn9965&oldid=84612"
Facts about "ThunderX2 CN9965 - Cavium"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
ThunderX2 CN9965 - Cavium#pcie +
base frequency1,800 MHz (1.8 GHz, 1,800,000 kHz) +, 2,000 MHz (2 GHz, 2,000,000 kHz) +, 2,100 MHz (2.1 GHz, 2,100,000 kHz) +, 2,200 MHz (2.2 GHz, 2,200,000 kHz) +, 2,300 MHz (2.3 GHz, 2,300,000 kHz) +, 2,400 MHz (2.4 GHz, 2,400,000 kHz) + and 2,500 MHz (2.5 GHz, 2,500,000 kHz) +
core count20 +
designerCavium +
familyThunderX2 +
first announcedMay 7, 2018 +
first launchedMay 7, 2018 +
full page namecavium/thunderx2/cn9965 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8.1 +
isa familyARM +
l1$ size1,280 KiB (1,310,720 B, 1.25 MiB) +
l1d$ description8-way set associative +
l1d$ size640 KiB (655,360 B, 0.625 MiB) +
l1i$ description8-way set associative +
l1i$ size640 KiB (655,360 B, 0.625 MiB) +
l2$ description8-way set associative +
l2$ size5 MiB (5,120 KiB, 5,242,880 B, 0.00488 GiB) +
l3$ size20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) +
ldateMay 7, 2018 +
manufacturerTSMC +
market segmentServer +
max cpu count2 +
max memory2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max sata ports2 +
max usb ports2 +
microarchitectureVulcan +
model numberCN9965 +
nameThunderX2 CN9965 +
packageFCLGA-4077 +
part numberCN9965-2500LG4077-Y21-G +, CN9965-2400LG4077-Y21-G +, CN9965-2300LG4077-Y21-G +, CN9965-2200LG4077-Y21-G +, CN9965-2100LG4077-Y21-G +, CN9965-2000LG4077-Y21-G + and CN9965-1800LG4077-Y21-G +
process16 nm (0.016 μm, 1.6e-5 mm) +
smp max ways2 +
supported memory typeDDR4-2666 +
technologyCMOS +
thread count40 +
word size64 bit (8 octets, 16 nibbles) +