Semiconductor & Computer Engineering
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Difference between revisions of "intel/cores/cascade lake ap"
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{{core | {{core | ||
|name=Cascade Lake AP | |name=Cascade Lake AP | ||
| + | |no image=Yes | ||
|developer=Intel | |developer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
Revision as of 13:19, 10 June 2018
| Edit Values | |
| Cascade Lake AP | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Microarchitecture | |
| ISA | x86-64 |
| Microarchitecture | Cascade Lake |
| Platform | Purley |
| Chipset | Lewisburg |
| Word Size | 8 octets 64 bit16 nibbles |
| Process | 14 nm 0.014 μm 1.4e-5 mm |
| Technology | CMOS |
| Packaging | |
| Unknown package "intel,bga_5903" | |
Cascade Lake AP is a pllaned series of server multiprocessors based on the Cascade Lake microarchitecture as part of the Purley platform.
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Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Facts about "Cascade Lake AP - Cores - Intel"
| chipset | Lewisburg + |
| designer | Intel + |
| instance of | core + |
| isa | x86-64 + |
| manufacturer | Intel + |
| microarchitecture | Cascade Lake + |
| name | Cascade Lake AP + |
| platform | Purley + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |