From WikiChip
Difference between revisions of "apm/microarchitectures/skylark"
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|successor=Quicksilver | |successor=Quicksilver | ||
− | |successor link=ampere computing/microarchitectures/ | + | |successor link=ampere computing/microarchitectures/ampere computing/microarchitectures/quicksilver |
}} | }} |
Revision as of 03:40, 9 February 2018
Edit Values | |
Skylark µarch | |
General Info | |
Arch Type | CPU |
Designer | AppliedMicro, Ampere Computing |
Manufacturer | TSMC |
Introduction | 2018 |
Process | 16 nm |
Core Configs | 32 |
Pipeline | |
Type | Superscalar |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Instructions | |
ISA | ARMv8 |
Succession | |
Facts about "Skylark - Microarchitectures - AppliedMicro"
codename | Skylark + |
core count | 32 + |
designer | AppliedMicro + and Ampere Computing + |
first launched | 2018 + |
full page name | apm/microarchitectures/skylark + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Skylark + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |