From WikiChip
Difference between revisions of "ampere computing/emag/8180"
< ampere computing‎ | emag

Line 29: Line 29:
 
}}
 
}}
 
'''A1''' is a {{arch|64}} [[32-core]] [[ARM]] server microprocessor introduced by [[ampere computing|Ampere]] in [[2018]]. Fabricated on [[TSMC]]'s [[16 nm process|16FF+]], this processor operates at ? with a turbo frequency of up to 3.3 GHz and 125 W TDP. This processor supports up to 8 channels of DDR4-2666 ECC memory.
 
'''A1''' is a {{arch|64}} [[32-core]] [[ARM]] server microprocessor introduced by [[ampere computing|Ampere]] in [[2018]]. Fabricated on [[TSMC]]'s [[16 nm process|16FF+]], this processor operates at ? with a turbo frequency of up to 3.3 GHz and 125 W TDP. This processor supports up to 8 channels of DDR4-2666 ECC memory.
 +
 +
{{unknown features}}
 +
 +
 +
== Cache ==<!--
 +
{{main|ampere_computing/microarchitectures/????????#Memory_Hierarchy|l1=???? § Cache}}-->
 +
{{cache size
 +
|l1 cache=2 MiB
 +
|l1i cache=1 MiB
 +
|l1i break=32x32 KiB
 +
|l1d cache=1 MiB
 +
|l1d break=32x32 KiB
 +
|l1d policy=write-through
 +
|l2 cache=4 MiB
 +
|l2 break=16x256 KiB
 +
|l3 cache=32 MiB
 +
|l3 break=1x32 MiB
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2666
 +
|type 2=DDR4-2400
 +
|ecc=Yes
 +
|max mem=1 TiB
 +
|controllers=8
 +
|channels=8
 +
|max bandwidth=158.95 GiB/s
 +
|bandwidth schan=19.89 GiB/s
 +
|bandwidth dchan=39.72 GiB/s
 +
|bandwidth qchan=79.47 GiB/s
 +
|bandwidth ochan=158.95 GiB/s
 +
|bandwidth hchan=119.21 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=48
 +
|pcie config=x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 +
}}
 +
}}

Revision as of 03:45, 7 February 2018

a1

Edit Values
A1
ampere a1.png
General Info
DesignerAmpere Computing
ManufacturerTSMC
Model NumberA1
MarketServer
IntroductionFebruary 5, 2018 (announced)
Release Price$950
General Specs
Turbo Frequency3,300 MHz
Microarchitecture
ISAARMv8 (ARM)
Process16 nm
TechnologyCMOS
Word Size64 bit
Cores32
Threads32
Max Memory1 TiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore0.85 V
VI/O1.8, 3.3
TDP125 W
Tjunction0 °C – 90 °C
Packaging
PackageFCBGA-3211 (BGA)
Dimension50 mm x 50 mm
Contacts3,211

A1 is a 64-bit 32-core ARM server microprocessor introduced by Ampere in 2018. Fabricated on TSMC's 16FF+, this processor operates at ? with a turbo frequency of up to 3.3 GHz and 125 W TDP. This processor supports up to 8 channels of DDR4-2666 ECC memory.

DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$2 MiB
2,048 KiB
2,097,152 B
L1I$1 MiB
1,024 KiB
1,048,576 B
32x32 KiB  
L1D$1 MiB
1,024 KiB
1,048,576 B
32x32 KiB write-through

L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  16x256 KiB  

L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  1x32 MiB  

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666, DDR4-2400
Supports ECCYes
Max Mem1 TiB
Controllers8
Channels8
Max Bandwidth158.95 GiB/s
162,764.8 MiB/s
170.671 GB/s
170,671.263 MB/s
0.155 TiB/s
0.171 TB/s
Bandwidth
Single 19.89 GiB/s
Double 39.72 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s
Octa 158.95 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: x16, x8, x4
Facts about "eMAG 8180 - Ampere"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
eMAG 8180 - Ampere#package + and eMAG 8180 - Ampere#pcie +
base frequency3,000 MHz (3 GHz, 3,000,000 kHz) +
core count32 +
core voltage0.85 V (8.5 dV, 85 cV, 850 mV) +
designerAmpere Computing +
familyeMAG +
first announcedFebruary 5, 2018 +
first launchedSeptember 8, 2018 +
full page nameampere computing/emag/8180 +
has ecc memory supporttrue +
instance ofmicroprocessor +
io voltage1.8 V (18 dV, 180 cV, 1,800 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv8 +
isa familyARM +
l1$ size2,048 KiB (2,097,152 B, 2 MiB) +
l1d$ size1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ size1,024 KiB (1,048,576 B, 1 MiB) +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldateSeptember 8, 2018 +
main imageFile:emag (front).jpg +
manufacturerTSMC +
market segmentServer +
max cpu count1 +
max junction temperature363.15 K (90 °C, 194 °F, 653.67 °R) +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) +
max memory channels8 +
max sata ports4 +
max usb ports2 +
microarchitectureSkylark +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number8180 +
nameeMAG 8180 +
packageFCBGA-3211 +
process16 nm (0.016 μm, 1.6e-5 mm) +
release price$ 850.00 (€ 765.00, £ 688.50, ¥ 87,830.50) +
serieseMAG 1 +
smp max ways1 +
supported memory typeDDR4-2666 + and DDR4-2400 +
tdp125 W (125,000 mW, 0.168 hp, 0.125 kW) +
technologyCMOS +
thread count32 +
turbo frequency3,300 MHz (3.3 GHz, 3,300,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +