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'''A1''' is a {{arch|64}} [[32-core]] [[ARM]] server microprocessor introduced by [[ampere computing|Ampere]] in [[2018]]. Fabricated on [[TSMC]]'s [[16 nm process|16FF+]], this processor operates at ? with a turbo frequency of up to 3.3 GHz and 125 W TDP. This processor supports up to 8 channels of DDR4-2666 ECC memory.
 
'''A1''' is a {{arch|64}} [[32-core]] [[ARM]] server microprocessor introduced by [[ampere computing|Ampere]] in [[2018]]. Fabricated on [[TSMC]]'s [[16 nm process|16FF+]], this processor operates at ? with a turbo frequency of up to 3.3 GHz and 125 W TDP. This processor supports up to 8 channels of DDR4-2666 ECC memory.
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{{unknown features}}
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== Cache ==<!--
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{{main|ampere_computing/microarchitectures/????????#Memory_Hierarchy|l1=???? § Cache}}-->
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{{cache size
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|l1 cache=2 MiB
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|l1i cache=1 MiB
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|l1i break=32x32 KiB
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|l1d cache=1 MiB
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|l1d break=32x32 KiB
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|l1d policy=write-through
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|l2 cache=4 MiB
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|l2 break=16x256 KiB
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|l3 cache=32 MiB
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|l3 break=1x32 MiB
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}}
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== Memory controller ==
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{{memory controller
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|type=DDR4-2666
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|type 2=DDR4-2400
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|ecc=Yes
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|max mem=1 TiB
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|controllers=8
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|channels=8
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|max bandwidth=158.95 GiB/s
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|bandwidth schan=19.89 GiB/s
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|bandwidth dchan=39.72 GiB/s
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|bandwidth qchan=79.47 GiB/s
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|bandwidth ochan=158.95 GiB/s
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|bandwidth hchan=119.21 GiB/s
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}}
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== Expansions ==
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{{expansions main
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|
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{{expansions entry
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|type=PCIe
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|pcie revision=3.0
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|pcie lanes=48
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|pcie config=x16
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|pcie config 2=x8
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|pcie config 3=x4
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}}
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}}

Revision as of 03:45, 7 February 2018

a1

Edit Values
A1
ampere a1.png
General Info
DesignerAmpere Computing
ManufacturerTSMC
Model NumberA1
MarketServer
IntroductionFebruary 5, 2018 (announced)
Release Price$950
General Specs
Turbo Frequency3,300 MHz
Microarchitecture
ISAARMv8 (ARM)
Process16 nm
TechnologyCMOS
Word Size64 bit
Cores32
Threads32
Max Memory1 TiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore0.85 V
VI/O1.8, 3.3
TDP125 W
Tjunction0 °C – 90 °C
Packaging
PackageFCBGA-3211 (BGA)
Dimension50 mm x 50 mm
Contacts3,211

A1 is a 64-bit 32-core ARM server microprocessor introduced by Ampere in 2018. Fabricated on TSMC's 16FF+, this processor operates at ? with a turbo frequency of up to 3.3 GHz and 125 W TDP. This processor supports up to 8 channels of DDR4-2666 ECC memory.

DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$2 MiB
2,048 KiB
2,097,152 B
L1I$1 MiB
1,024 KiB
1,048,576 B
32x32 KiB  
L1D$1 MiB
1,024 KiB
1,048,576 B
32x32 KiB write-through
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  16x256 KiB  
L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  1x32 MiB  

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666, DDR4-2400
Supports ECCYes
Max Mem1 TiB
Controllers8
Channels8
Max Bandwidth158.95 GiB/s
162,764.8 MiB/s
170.671 GB/s
170,671.263 MB/s
0.155 TiB/s
0.171 TB/s
Bandwidth
Single 19.89 GiB/s
Double 39.72 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s
Octa 158.95 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: x16, x8, x4
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