Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "esperanto/microarchitectures/et-minion"
| Line 22: | Line 22: | ||
|contemporary link=esperanto/microarchitectures/et-maxion | |contemporary link=esperanto/microarchitectures/et-maxion | ||
}} | }} | ||
| − | '''ET-Minion''' is | + | '''ET-Minion''' is an energy-efficienct [[RISC-V]] microarchitecture designed by [[Esperanto]]. ET-Minion is also sold as a licensable [[synthesizable]] [[IP core]]. |
Revision as of 20:28, 25 December 2017
| Edit Values | |
| ET-Minion µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Esperanto |
| Manufacturer | TSMC |
| Introduction | 2018 |
| Process | 7 nm |
| Pipeline | |
| Type | Superscalar, Pipelined |
| OoOE | No |
| Speculative | Yes |
| Reg Renaming | No |
| Instructions | |
| ISA | RV64 |
| Extensions | I, M, A, F, D, C |
| Contemporary | |
| ET-Maxion | |
ET-Minion is an energy-efficienct RISC-V microarchitecture designed by Esperanto. ET-Minion is also sold as a licensable synthesizable IP core.
Facts about "ET-Minion - Microarchitectures - Esperanto"
| codename | ET-Minion + |
| designer | Esperanto + |
| first launched | 2018 + |
| full page name | esperanto/microarchitectures/et-minion + |
| instance of | microarchitecture + |
| instruction set architecture | RV64 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | ET-Minion + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + |