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Difference between revisions of "intel/core i3/i3-9100t"
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'''Core i3-9100T''' is a planned {{arch|64}} mid-range performance [[x86]] desktop processor by [[Intel]] set to be introduced in [[2018]]/2019. The i3-9100T is fabricated on Intel's 2nd generation [[10 nm process|10nm+ process]] based on the {{intel|Ice Lake|l=arch}} microarchitecture.
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'''Core i3-9100T''' is a planned {{arch|64}} mid-range performance [[x86]] desktop processor by [[Intel]] set to be introduced in late [[2018]]. The i3-9100T is fabricated on Intel's enhanced [[14 nm process|14nm++ process]] based on the {{intel|Coffee Lake|l=arch}} microarchitecture.
  
  

Revision as of 12:43, 1 February 2018

Edit Values
Core i3-9100T
General Info
DesignerIntel
ManufacturerIntel
Model Numberi3-9100T
MarketDesktop
ShopAmazon
General Specs
FamilyCore i3
Seriesi3-9000
LockedYes
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCoffee Lake
Core NameCoffee Lake R
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores4
Threads8
Max Memory64 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP35 W

Core i3-9100T is a planned 64-bit mid-range performance x86 desktop processor by Intel set to be introduced in late 2018. The i3-9100T is fabricated on Intel's enhanced 14nm++ process based on the Coffee Lake microarchitecture.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Water drop.svg Leaked Info! Some of the information presented in this article is solely based on leaks that were published online or obtained directly by WikiChip. It goes without saying that this information could change, be incomplete, wrong, or even made up. It's highly advised to wait for an official product announcement.


Cache

Main article: Ice Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB4-way set associativewrite-back
L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiB16-way set associativewrite-back
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i3/i3-9100t&oldid=73388"
Facts about "Core i3-9100T - Intel"
RDF feed
core count4 +
core nameCoffee Lake R +
designerIntel +
familyCore i3 +
full page nameintel/core i3/i3-9100t +
has locked clock multipliertrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description16-way set associative +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldate3000 +
manufacturerIntel +
market segmentDesktop +
max cpu count1 +
max memory65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
microarchitectureCoffee Lake +
model numberi3-9100T +
nameCore i3-9100T +
process14 nm (0.014 μm, 1.4e-5 mm) +
seriesi3-9000 +
smp max ways1 +
tdp35 W (35,000 mW, 0.0469 hp, 0.035 kW) +
technologyCMOS +
thread count8 +
word size64 bit (8 octets, 16 nibbles) +