From WikiChip
Difference between revisions of "intel/core i7/i7-8850h"
< intel‎ | core i7

Line 32: Line 32:
  
 
{{unknown features}}
 
{{unknown features}}
 +
 +
 +
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/coffee_lake#Memory_Hierarchy|l1=Coffee Lake § Cache}}
 +
{{cache size
 +
|l1 cache=386 KiB
 +
|l1i cache=192 KiB
 +
|l1i break=6x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=192 KiB
 +
|l1d break=6x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=1.5 MiB
 +
|l2 break=6x256 KiB
 +
|l2 desc=4-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=12 MiB
 +
|l3 break=6x2 MiB
 +
|l3 desc=16-way set associative
 +
|l3 policy=write-back
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2666
 +
|ecc=No
 +
|max mem=64 GiB
 +
|controllers=1
 +
|channels=2
 +
|max bandwidth=39.74 GiB/s
 +
|bandwidth schan=19.87 GiB/s
 +
|bandwidth dchan=39.74 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=16
 +
|pcie config=1x16
 +
|pcie config 2=2x8
 +
|pcie config 3=1x8+2x4
 +
}}
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=No
 +
|avx512cd=No
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=No
 +
|avx512dq=No
 +
|avx512vl=No
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=Yes
 +
|att=No
 +
|ipt=Yes
 +
|tsx=No
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=Yes
 +
|sgx=Yes
 +
|securekey=Yes
 +
|osguard=Yes
 +
|intqat=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
}}

Revision as of 17:02, 24 November 2017

Template:mpu Core i7-8850H is a 64-bit hexa-core high-end performance x86 mobile microprocessor set to be introduced by Intel in 2018. This processor, which is based on the Coffee Lake microarchitecture, is manufactured on Intel's 3rd generation enhanced 14nm++ process.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.



Cache

Main article: Coffee Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$386 KiB
395,264 B
0.377 MiB
L1I$192 KiB
196,608 B
0.188 MiB
6x32 KiB8-way set associative 
L1D$192 KiB
196,608 B
0.188 MiB
6x32 KiB8-way set associativewrite-back
L2$1.5 MiB
1,536 KiB
1,572,864 B
0.00146 GiB
  6x256 KiB4-way set associativewrite-back
L3$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  6x2 MiB16-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCNo
Max Mem64 GiB
Controllers1
Channels2
Max Bandwidth39.74 GiB/s
40,693.76 MiB/s
42.671 GB/s
42,670.5 MB/s
0.0388 TiB/s
0.0427 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 16
Configuration: 1x16, 2x8, 1x8+2x4


Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
MPXMemory Protection Extensions
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
SIPPStable Image Platform Program
IPTIdentity Protection Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i7/i7-8850h&oldid=67867"
Facts about "Core i7-8850H - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Core i7-8850H - Intel#pcie +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supportfalse +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Stable Image Platform Program + and Identity Protection Technology +
has intel enhanced speedstep technologytrue +
has intel identity protection technology supporttrue +
has intel secure key technologytrue +
has intel stable image platform program supporttrue +
has intel supervisor mode execution protectiontrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size386 KiB (395,264 B, 0.377 MiB) +
l1d$ description8-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description8-way set associative +
l1i$ size192 KiB (196,608 B, 0.188 MiB) +
l2$ description4-way set associative +
l2$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l3$ description16-way set associative +
l3$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
max memory bandwidth39.74 GiB/s (40,693.76 MiB/s, 42.671 GB/s, 42,670.5 MB/s, 0.0388 TiB/s, 0.0427 TB/s) +
max memory channels2 +
supported memory typeDDR4-2666 +
x86/has memory protection extensionstrue +
x86/has software guard extensionstrue +