Semiconductor & Computer Engineering
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Difference between revisions of "hisilicon/k3/k3v2e"
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|part number=Hi3620 | |part number=Hi3620 | ||
|market=Mobile | |market=Mobile | ||
| − | |first announced= | + | |first announced=2013 |
| − | |first launched= | + | |first launched=2013 |
|family=K3 | |family=K3 | ||
|frequency=1,500 MHz | |frequency=1,500 MHz | ||
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|package module 1={{packages/hisilicon/tfbga-576}} | |package module 1={{packages/hisilicon/tfbga-576}} | ||
}} | }} | ||
| − | '''K3V2E''' is a {{arch|32}} [[quad-core]] mobile [[ARM]] microprocessor introduced by [[HiSilicon]] in | + | '''K3V2E''' is a {{arch|32}} [[quad-core]] mobile [[ARM]] microprocessor introduced by [[HiSilicon]] in [[2013]]. This chip, which is fabricated on a [[40 nm process]], incorporates four {{armh|Cortex-A9|l=arch}} cores operating at 1.5 GHz. The K3V2 integrated [[Vivante]]'s {{vivante|GC4000}} (16 cores) [[IGP]] and supports up to 2 channels of LPDDR2-900 memory. The K3V2E is an enhanced version of the {{\\|K3V2}}, although the exact changes are not well-documented. |
Revision as of 21:43, 6 September 2017
Template:mpu K3V2E is a 32-bit quad-core mobile ARM microprocessor introduced by HiSilicon in 2013. This chip, which is fabricated on a 40 nm process, incorporates four Cortex-A9 cores operating at 1.5 GHz. The K3V2 integrated Vivante's GC4000 (16 cores) IGP and supports up to 2 channels of LPDDR2-900 memory. The K3V2E is an enhanced version of the K3V2, although the exact changes are not well-documented.
Cache
- Main article: Cortex-A9 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Graphics
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Integrated Graphics Information
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Expansions
- 4x high-speed UART interfaces
- 2x SPI
- 2x I2C + 2x I2C for camera
- USB 2.0 On-The-Go (HS OTG) PHY
- USB 1.1
- 2x MMC/SD/SDIO interface
- 22x GPIOs
- 10 Timers
Block Diagram
Utilizing devices
- Huawei HN3-U01
- Huawei Ascend P6 (P6-C00)
- Ascend W2 (W2‐T00)
- Huawei Honor 3
This list is incomplete; you can help by expanding it.
Facts about "K3V2E - HiSilicon"
| has ecc memory support | false + |
| integrated gpu | GC4000 + |
| integrated gpu base frequency | 480 MHz (0.48 GHz, 480,000 KHz) + |
| integrated gpu designer | Vivante + |
| integrated gpu execution units | 16 + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| max memory bandwidth | 6.71 GiB/s (6,871.04 MiB/s, 7.205 GB/s, 7,204.808 MB/s, 0.00655 TiB/s, 0.0072 TB/s) + |
| max memory channels | 2 + |
| supported memory type | LPDDR2-900 + |
| used by | Huawei HN3-U01 +, Huawei Ascend P6 +, Ascend W2 + and Huawei Honor 3 + |