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Difference between revisions of "intel/xeon w/w-2104"
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'''W-2104''' is a {{arch|64}} [[quad-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2017]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake}} server microarchitecture, operates at 3.2 GHz with a [[TDP]] of 120 W and no {{intel|turbo boost}}. This chip supports up to 512 GiB of quad-channel DDR4-2400 ECC memory. | '''W-2104''' is a {{arch|64}} [[quad-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2017]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake}} server microarchitecture, operates at 3.2 GHz with a [[TDP]] of 120 W and no {{intel|turbo boost}}. This chip supports up to 512 GiB of quad-channel DDR4-2400 ECC memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} | ||
+ | Note that while this is a [[quad-core]] part, the [[L3 cache]] size is that of a [[hexa-core]] part. | ||
+ | {{cache size | ||
+ | |l1 cache=256 KiB | ||
+ | |l1i cache=128 KiB | ||
+ | |l1i break=4x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=128 KiB | ||
+ | |l1d break=4x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=4 MiB | ||
+ | |l2 break=4x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=8.25 MiB | ||
+ | |l3 break=6x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2400 | ||
+ | |ecc=Yes | ||
+ | |max mem=512 GiB | ||
+ | |controllers=2 | ||
+ | |channels=4 | ||
+ | |max bandwidth=71.53 GiB/s | ||
+ | |bandwidth schan=17.88 GiB/s | ||
+ | |bandwidth dchan=35.76 GiB/s | ||
+ | |bandwidth qchan=71.53 GiB/s | ||
+ | |pae=46 bit | ||
+ | }} |
Revision as of 01:44, 6 September 2017
Template:mpu W-2104 is a 64-bit quad-core x86 enterprise performance workstation microprocessor introduced by Intel in 2017. This processors, which is fabricated on an enhanced 14nm+ process based on the Skylake server microarchitecture, operates at 3.2 GHz with a TDP of 120 W and no turbo boost. This chip supports up to 512 GiB of quad-channel DDR4-2400 ECC memory.
Cache
- Main article: Skylake § Cache
Note that while this is a quad-core part, the L3 cache size is that of a hexa-core part.
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Facts about "Xeon W-2104 - Intel"
has ecc memory support | true + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 8.25 MiB (8,448 KiB, 8,650,752 B, 0.00806 GiB) + |
max memory bandwidth | 71.53 GiB/s (73,246.72 MiB/s, 76.805 GB/s, 76,804.753 MB/s, 0.0699 TiB/s, 0.0768 TB/s) + |
max memory channels | 4 + |
supported memory type | DDR4-2400 + |