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Difference between revisions of "intel/microarchitectures/goldmont plus"
| Line 59: | Line 59: | ||
=== Block Diagram === | === Block Diagram === | ||
{{empty section}} | {{empty section}} | ||
| + | === Memory Hierarchy === | ||
| + | * Cache | ||
| + | ** Hardware prefetchers | ||
| + | ** L1 Cache: | ||
| + | *** 32 [[KiB]] 8-way [[set associative]] instruction, 64 B line size | ||
| + | *** 24 KiB 6-way set associative data, 64 B line size | ||
| + | *** Per core | ||
| + | ** L2 Cache: | ||
| + | *** 2 MiB 16-way set associative, 64 B line size | ||
| + | *** Per 2 cores | ||
| + | ** L3 Cache: | ||
| + | *** No level 3 cache | ||
| + | ** RAM | ||
| + | *** Maximum of 1 [[GiB]], 2 GiB, 4 GiB, 8 GiB | ||
| + | *** dual 32-bit channels, 1 or 2 ranks per channel | ||
| + | === Multithreading === | ||
| + | Goldmont Plus, like {{\\|Goldmont}} has no support for Intel Hyper-Threading Technology. | ||
== Core == | == Core == | ||
{{empty section}} | {{empty section}} | ||
Revision as of 01:27, 27 July 2017
| Edit Values | |
| Goldmont Plus µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2017 |
| Process | 14 nm |
| Core Configs | 2, 4 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-16, x86-32, x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA |
| Cache | |
| L1I Cache | 32 KiB/Core 8-way set associative |
| L1D Cache | 24 KiB/Core 6-way set associative |
| L2 Cache | 2 MiB/2 Cores 16-way set associative |
| Cores | |
| Core Names | Gemini Lake |
| Succession | |
Goldmont Plus is Intel's 14 nm microarchitecture of system on chips for the ultra-low power (ULP) devices serving as a successor to Goldmont. Goldmont Plus-based processors and SoCs are part of the Atom, Pentium, and Celeron families.
Contents
Codenames
| Platform | Core | Target |
|---|---|---|
| Gemini Lake | Gemini Lake | Tablets, Entry-level PCs, Communications, Storage |
Architecture
Key changes from Goldmont
- 4-way decode (from 3-way)[1]
- Integrated native HDMI 2.0 controller
- Integrated Intel wireless controller (IEEE 802.11ac)
Block Diagram
 |
This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy
- Cache
- Hardware prefetchers
- L1 Cache:
- 32 KiB 8-way set associative instruction, 64 B line size
- 24 KiB 6-way set associative data, 64 B line size
- Per core
- L2 Cache:
- 2 MiB 16-way set associative, 64 B line size
- Per 2 cores
- L3 Cache:
- No level 3 cache
- RAM
- Maximum of 1 GiB, 2 GiB, 4 GiB, 8 GiB
- dual 32-bit channels, 1 or 2 ranks per channel
Multithreading
Goldmont Plus, like Goldmont has no support for Intel Hyper-Threading Technology.
Core
| |
This section is empty; you can help add the missing info by editing this page. |
Facts about "Goldmont Plus - Microarchitectures - Intel"
| codename | Goldmont Plus + |
| core count | 2 + and 4 + |
| designer | Intel + |
| first launched | 2017 + |
| full page name | intel/microarchitectures/goldmont plus + |
| instance of | microarchitecture + |
| instruction set architecture | x86-16 +, x86-32 + and x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Goldmont Plus + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |