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Difference between revisions of "intel/microarchitectures/goldmont plus"
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(Created page with "{{intel title|Goldmont Plus|arch}} {{microarchitecture |atype=CPU |name=Goldmont |designer=Intel |manufacturer=Intel |introduction=August 30, 2016 |process=14 nm |cores=2 |co...")
 
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{{microarchitecture
 
{{microarchitecture
 
|atype=CPU
 
|atype=CPU
|name=Goldmont
+
|name=Goldmont Plus
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
|introduction=August 30, 2016
 
 
|process=14 nm
 
|process=14 nm
 
|cores=2
 
|cores=2
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|cores 3=8
 
|cores 3=8
 
|type=Superscalar
 
|type=Superscalar
 +
|oooe=Yes
 
|speculative=Yes
 
|speculative=Yes
 
|renaming=Yes
 
|renaming=Yes
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|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|core name=Apollo Lake
 
|core name=Apollo Lake
|predecessor=Airmont
+
|predecessor=Goldmont
|predecessor link=intel/microarchitectures/airmont
+
|predecessor link=intel/microarchitectures/goldmont
|successor=Goldmont Plus
 
|successor link=intel/microarchitectures/goldmont plus
 
 
}}
 
}}

Revision as of 19:20, 25 July 2017


Edit Values
Goldmont Plus µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Process14 nm
Core Configs2, 4, 8
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages12-14
Instructions
ISAIA-32, x86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA
Cache
L1I Cache32 KiB/Core
8-way set associative
L1D Cache24 KiB/Core
6-way set associative
L2 Cache1 MiB/2 Cores
16-way set associative
Cores
Core NamesApollo Lake
Succession
codenameGoldmont Plus +
core count2 +, 4 + and 8 +
designerIntel +
full page nameintel/microarchitectures/goldmont plus +
instance ofmicroarchitecture +
instruction set architectureIA-32 + and x86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameGoldmont Plus +
pipeline stages (max)14 +
pipeline stages (min)12 +
process14 nm (0.014 μm, 1.4e-5 mm) +