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Difference between revisions of "renesas/r-car/m1s"
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'''R-Car M1S''' is a mid-range performance embedded [[single-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The M1S features a single {{renesas|SH-4A|l=arch}} core operating at 800 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory. | '''R-Car M1S''' is a mid-range performance embedded [[single-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The M1S features a single {{renesas|SH-4A|l=arch}} core operating at 800 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=128 KiB | ||
+ | |l1i cache=64 KiB | ||
+ | |l1i break=2x32 KiB | ||
+ | |l1i desc=4-way set associative | ||
+ | |l1d cache=64 KiB | ||
+ | |l1d break=2x32 KiB | ||
+ | |l1d desc=4-way set associative | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR3-1066 | ||
+ | |type=DDR2-800 | ||
+ | |ecc=No | ||
+ | |max mem=1 GiB | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=32 bit | ||
+ | |max bandwidth=3.97 GiB/s | ||
+ | |bandwidth schan=3.97 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | usb revision = 2.0 | ||
+ | | usb ports = 2 | ||
+ | | usb rate = 480 Mbps | ||
+ | | uart = Yes | ||
+ | | uart ports = 8 | ||
+ | | sata revision = 3.0 | ||
+ | | sata ports = 1 | ||
+ | | i2c = Yes | ||
+ | | i2c ports = 4 | ||
+ | | gp io = Yes | ||
+ | | jtag = Yes | ||
+ | }} | ||
+ | * MLB (MOST150) 6-Pin I/F | ||
+ | * 2 x CAN 32 Message Buffers | ||
+ | * MMC | ||
+ | * 3 x SD | ||
+ | |||
+ | == Graphics == | ||
+ | * 20MPoly/s; 1000MPix/s; 3.2GFlops/s | ||
+ | {{integrated graphics | ||
+ | | gpu = PowerVR SGX540 | ||
+ | | designer = Imagination Technologies | ||
+ | | execution units = 2 | ||
+ | | max displays = 2 | ||
+ | | frequency = 200 MHz | ||
+ | |||
+ | | opengl es ver = 2.0 | ||
+ | | opengl ver = 2.1 | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{arm features | ||
+ | |thumb=No | ||
+ | |thumb2=Yes | ||
+ | |thumbee=Yes | ||
+ | |vfpv1=No | ||
+ | |vfpv2=No | ||
+ | |vfpv3=Yes | ||
+ | |vfpv3-d16=No | ||
+ | |vfpv3-f16=No | ||
+ | |vfpv4=No | ||
+ | |vfpv4-d16=No | ||
+ | |vfpv5=No | ||
+ | |neon=Yes | ||
+ | |jazelle=Yes | ||
+ | |wmmx=No | ||
+ | |wmmx2=No | ||
+ | }} |
Revision as of 10:18, 21 July 2017
Template:mpu R-Car M1S is a mid-range performance embedded single-core SoC for the automotive industry designed by Renesas and introduced in 2011. The M1S features a single SH-4A core operating at 800 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory.
Cache
- Main article: Cortex-A9 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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- MLB (MOST150) 6-Pin I/F
- 2 x CAN 32 Message Buffers
- MMC
- 3 x SD
Graphics
- 20MPoly/s; 1000MPix/s; 3.2GFlops/s
Integrated Graphics Information
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Features
[Edit/Modify Supported Features]
Supported ARM Extensions & Processor Features
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Facts about "R-Car M1S - Renesas"
has ecc memory support | false + |
integrated gpu | PowerVR SGX540 + |
integrated gpu base frequency | 200 MHz (0.2 GHz, 200,000 KHz) + |
integrated gpu designer | Imagination Technologies + |
integrated gpu execution units | 2 + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
max memory bandwidth | 3.97 GiB/s (4,065.28 MiB/s, 4.263 GB/s, 4,262.755 MB/s, 0.00388 TiB/s, 0.00426 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR2-800 + |