Revision as of 10:08, 21 July 2017

Template:mpu R-Car H1 is a high-end embedded penta-core SoC for the automotive industry designed by Renesas and introduced in 2011. While mass production was scheduled to begin in December 2012, it's unknown if that stage was ever actually reached. The H1 features 5 cores, four Cortex-A9 cores operating at 1 GHz and an additional SH-4A core operating at 800 MHz intended for real-time processing multimedia engine (MME). This chip incorporates Imagination's PowerVR SGX543-MP2 GPU. The H1 supports up to 2 GiB of dual-channel DDR3-1066 memory.

Cache

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 4-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 4-way set associative   L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     4x256 KiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1066 Supports ECC No Max Mem 2 GiB Controllers 1 Channels 2 Width 32 bit Max Bandwidth 7.95 GiB/s 8,140.8 MiB/s 8.536 GB/s 8,536.248 MB/s 0.00776 TiB/s 0.00854 TB/s Bandwidth Single 3.97 GiB/s Double 7.95 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
	PCIe Revision 2.0 Max Lanes 1 Configs 1x1 USB Revision 2.0 Ports 2 Rate 480 Mbps UART Ports 8 SATA Revision 3.0 Ports 1 I²C Ports 4 GP I/O Yes JTAG Yes

• 3 x HSPI
• MLB (MOST150) 6-Pin I/F
• 2 x CAN 32 Message Buffers
• MMC
• 4 x SD

Graphics

• Display out × 2 ch (RGB888)
• Video input x 2 ch
• Video decode processor (H.264/AVC, MPEG-4, VC-1)

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU PowerVR SGX543 Designer Imagination Technologies Execution Units 2 Max Displays 2 Frequency 250 MHz 0.25 GHz 250,000 KHz Standards OpenGL 2.0 OpenCL 1.1 OpenGL ES 2.0

Audio

• Sound processing unit × 2 ch
• Sampling rate converter × 10 ch
• Sound serial interface × 10 ch
• MOST DTCP

Features

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	Thumb-2 Thumb-2 Extension ThumbEE Thumb Execution Environment Extension VFPv3 Vector Floating Point (VFP) v3 Extension NEON Advanced SIMD extension Jazelle Direct Bytecode eXecution

Block Diagram