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    Difference between revisions of "intel/xeon gold/6154"    
                	
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| {{intel title|Xeon Gold 6154}} | {{intel title|Xeon Gold 6154}} | ||
| {{mpu | {{mpu | ||
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| |name=Xeon Gold 6154 | |name=Xeon Gold 6154 | ||
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| |image=skylake sp (basic).png | |image=skylake sp (basic).png | ||
| |designer=Intel | |designer=Intel | ||
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| |process=14 nm | |process=14 nm | ||
| |technology=CMOS | |technology=CMOS | ||
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| |word size=64 bit | |word size=64 bit | ||
| |core count=18 | |core count=18 | ||
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| |max cpus=4 | |max cpus=4 | ||
| |max memory=768 GiB | |max memory=768 GiB | ||
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| |tdp=200 W | |tdp=200 W | ||
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| |tcase min=0 °C | |tcase min=0 °C | ||
| |tcase max=82 °C | |tcase max=82 °C | ||
| |package module 1={{packages/intel/fclga-3647}} | |package module 1={{packages/intel/fclga-3647}} | ||
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| }} | }} | ||
| − | '''Xeon Gold 6154''' is a {{arch|64}} [[ | + | '''Xeon Gold 6154''' is a {{arch|64}} [[18-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6154, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3 GHz with a TDP of 200 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory. | 
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| == Cache == | == Cache == | ||
Revision as of 00:04, 12 July 2017
Template:mpu Xeon Gold 6154 is a 64-bit 18-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6154, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3 GHz with a TDP of 200 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Cache
- Main article: Skylake § Cache
|  | Cache Organization  Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. | ||||||||||||||||||||||||||||||||||||
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Memory controller
|  | Integrated Memory Controller | |||||||||||
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Features
[Edit/Modify Supported Features]
Facts about "Xeon Gold 6154  - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6154 - Intel#io +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel + and Xeon Gold 6154 - Intel + | 
| base frequency | 3,000 MHz (3 GHz, 3,000,000 kHz) + | 
| bus links | 4 + | 
| bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + | 
| bus type | DMI 3.0 + | 
| chipset | Lewisburg + | 
| clock multiplier | 30 + | 
| core count | 18 + | 
| core family | 6 + | 
| core name | Skylake SP + | 
| core stepping | H0 + | 
| cpuid | 0x50654 + | 
| designer | Intel + | 
| family | Xeon Gold + | 
| first announced | April 25, 2017 + | 
| first launched | July 11, 2017 + | 
| full page name | intel/xeon gold/6154 + | 
| has advanced vector extensions | true + | 
| has advanced vector extensions 2 | true + | 
| has advanced vector extensions 512 | true + | 
| has ecc memory support | true + | 
| has extended page tables support | true + | 
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions + | 
| has intel enhanced speedstep technology | true + | 
| has intel speed shift technology | true + | 
| has intel trusted execution technology | true + | 
| has intel turbo boost technology 2 0 | true + | 
| has intel vpro technology | true + | 
| has intel vt-d technology | true + | 
| has intel vt-x technology | true + | 
| has locked clock multiplier | true + | 
| has second level address translation support | true + | 
| has simultaneous multithreading | true + | 
| has transactional synchronization extensions | true + | 
| has x86 advanced encryption standard instruction set extension | true + | 
| instance of | microprocessor + | 
| isa | x86-64 + | 
| isa family | x86 + | 
| l1$ size | 1,152 KiB (1,179,648 B, 1.125 MiB) + | 
| l1d$ description | 8-way set associative + | 
| l1d$ size | 576 KiB (589,824 B, 0.563 MiB) + | 
| l1i$ description | 8-way set associative + | 
| l1i$ size | 576 KiB (589,824 B, 0.563 MiB) + | 
| l2$ description | 16-way set associative + | 
| l2$ size | 18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) + | 
| l3$ description | 11-way set associative + | 
| l3$ size | 24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) + | 
| ldate | July 11, 2017 + | 
| main image |  + | 
| manufacturer | Intel + | 
| market segment | Server + | 
| max case temperature | 355.15 K (82 °C, 179.6 °F, 639.27 °R) + | 
| max cpu count | 4 + | 
| max dts temperature | 106 °C + | 
| max memory | 786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) + | 
| max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + | 
| max memory channels | 6 + | 
| max pcie lanes | 48 + | 
| microarchitecture | Skylake (server) + | 
| min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + | 
| min dts temperature | 0 °C + | 
| model number | 6154 + | 
| name | Xeon Gold 6154 + | 
| package | FCLGA-3647 + | 
| part number | CD8067303592700 + | 
| platform | Purley + | 
| process | 14 nm (0.014 μm, 1.4e-5 mm) + | 
| release price | $ 3,543.00 (€ 3,188.70, £ 2,869.83, ¥ 366,098.19) + | 
| s-spec | SR3J5 + | 
| s-spec (qs) | QMQ9 + | 
| series | 6100 + | 
| smp interconnect | UPI + | 
| smp interconnect links | 3 + | 
| smp interconnect rate | 10.4 GT/s + | 
| smp max ways | 4 + | 
| socket | Socket P + and LGA-3647 + | 
| supported memory type | DDR4-2666 + | 
| tdp | 200 W (200,000 mW, 0.268 hp, 0.2 kW) + | 
| technology | CMOS + | 
| thread count | 36 + | 
| turbo frequency (1 core) | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + | 
| word size | 64 bit (8 octets, 16 nibbles) + | 
