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Difference between revisions of "intel/xeon gold/5115"
(Created page with "{{intel title|Xeon Gold 5115}} {{mpu |future=Yes |name=Xeon Gold 5115 |no image=Yes |designer=Intel |manufacturer=Intel |model number=5115 |part number=CD8067303535601 |market...") |
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{{intel title|Xeon Gold 5115}} | {{intel title|Xeon Gold 5115}} | ||
{{mpu | {{mpu | ||
− | |||
|name=Xeon Gold 5115 | |name=Xeon Gold 5115 | ||
− | | | + | |image=skylake sp (basic).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=5115 | |model number=5115 | ||
|part number=CD8067303535601 | |part number=CD8067303535601 | ||
+ | |s-spec=SR3GB | ||
|market=Server | |market=Server | ||
+ | |first announced=July 11, 2017 | ||
+ | |first launched=July 11, 2017 | ||
+ | |release price=$1221.00 | ||
|family=Xeon Gold | |family=Xeon Gold | ||
|series=5000 | |series=5000 | ||
|locked=Yes | |locked=Yes | ||
|frequency=2,400 MHz | |frequency=2,400 MHz | ||
+ | |turbo frequency1=3,200 MHz | ||
+ | |clock multiplier=24 | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
Line 20: | Line 25: | ||
|core name=Skylake SP | |core name=Skylake SP | ||
|core family=6 | |core family=6 | ||
+ | |core stepping=M0 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 25: | Line 31: | ||
|core count=10 | |core count=10 | ||
|thread count=20 | |thread count=20 | ||
+ | |max cpus=4 | ||
+ | |max memory=768 GiB | ||
+ | |tdp=85 W | ||
+ | |tcase min=0 °C | ||
+ | |tcase max=76 °C | ||
|package module 1={{packages/intel/fclga-3647}} | |package module 1={{packages/intel/fclga-3647}} | ||
}} | }} |
Revision as of 19:21, 11 July 2017
Template:mpu Xeon Gold 5115 is a 64-bit deca-core x86 server microprocessor set to be introduced by Intel in July 2017. This processor operates at 2.4 GHz.
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Xeon Gold 5115 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 5115 - Intel#io + |
base frequency | 2,400 MHz (2.4 GHz, 2,400,000 kHz) + |
chipset | Lewisburg + |
clock multiplier | 24 + |
core count | 10 + |
core family | 6 + |
core name | Skylake SP + |
core stepping | M0 + |
cpuid | 0x50654 + |
designer | Intel + |
family | Xeon Gold + |
first announced | July 11, 2017 + |
first launched | July 11, 2017 + |
full page name | intel/xeon gold/5115 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) + |
ldate | July 11, 2017 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 349.15 K (76 °C, 168.8 °F, 628.47 °R) + |
max cpu count | 4 + |
max dts temperature | 90 °C + |
max memory | 786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
microarchitecture | Skylake (server) + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min dts temperature | 0 °C + |
model number | 5115 + |
name | Xeon Gold 5115 + |
package | FCLGA-3647 + |
part number | CD8067303535601 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 1,221.00 (€ 1,098.90, £ 989.01, ¥ 126,165.93) + |
s-spec | SR3GB + |
s-spec (qs) | QMXG + |
series | 5100 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2400 + |
tdp | 85 W (85,000 mW, 0.114 hp, 0.085 kW) + |
technology | CMOS + |
thread count | 20 + |
turbo frequency (1 core) | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |