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Difference between revisions of "loongson/godson 2/2f"
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'''Godson-2F''' ('''龙芯2F''') is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in mid-[[2008]], the Godson-2F operates at up to 800 MHz consuming 5 W. This chip was manufactured on [[STMicroelectronics]]' [[90 nm process]].
 
'''Godson-2F''' ('''龙芯2F''') is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in mid-[[2008]], the Godson-2F operates at up to 800 MHz consuming 5 W. This chip was manufactured on [[STMicroelectronics]]' [[90 nm process]].
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== Cache ==
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{{main|loongson/microarchitectures/GS464#Memory_Hierarchy|l1=GS464 § Cache}}
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{{cache size
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|l1 cache=128 KiB
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|l1i cache=64 KiB
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|l1i break=1x64 KiB
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|l1i desc=4-way set associative
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|l1d cache=64 KiB
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|l1d break=1x64 KiB
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|l1d desc=4-way set associative
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|l1d policy=
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|l2 cache=512 KiB
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|l2 break=1x512 KiB
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|l2 desc=4-way set associative
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|l2 policy=
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}}
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== Memory controller ==
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{{memory controller
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|type=DDR2-667
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|ecc=Yes
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|max mem=4 GiB
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|controllers=1
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|channels=1
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|max bandwidth=9.934 GiB/s
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|bandwidth schan=9.934 GiB/s
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}}
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== Graphics ==
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This chip had no [[integrated graphics processing unit]].

Revision as of 15:36, 19 March 2017

Template:mpu Godson-2F (龙芯2F) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in mid-2008, the Godson-2F operates at up to 800 MHz consuming 5 W. This chip was manufactured on STMicroelectronics' 90 nm process.

Cache

Main article: GS464 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
1x64 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
1x64 KiB4-way set associative 
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB4-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-667
Supports ECCYes
Max Mem4 GiB
Controllers1
Channels1
Max Bandwidth9.934 GiB/s
10,172.416 MiB/s
10.667 GB/s
10,666.551 MB/s
0.0097 TiB/s
0.0107 TB/s
Bandwidth
Single 9.934 GiB/s



Graphics

This chip had no integrated graphics processing unit.

Retrieved from "https://en.wikichip.org/w/index.php?title=loongson/godson_2/2f&oldid=39891"
Facts about "Godson-2F - Loongson"
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has ecc memory supporttrue +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description4-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
max memory bandwidth9.934 GiB/s (10,172.416 MiB/s, 10.667 GB/s, 10,666.551 MB/s, 0.0097 TiB/s, 0.0107 TB/s) +
max memory channels1 +
supported memory typeDDR2-667 +