From WikiChip
Difference between revisions of "intel/core m/m5-6y54"
< intel‎ | core m

Line 2: Line 2:
 
{{mpu
 
{{mpu
 
| name                = Core M5-6Y54
 
| name                = Core M5-6Y54
−
| no image            = Yes
+
| no image            =  
−
| image              =  
+
| image              = skylake y (front).png
−
| image size          =  
+
| image size          = 250px
 
| caption            =  
 
| caption            =  
 
| designer            = Intel
 
| designer            = Intel
Line 15: Line 15:
 
| last order          =  
 
| last order          =  
 
| last shipment      =  
 
| last shipment      =  
 +
| release price      = $281
  
 
| family              = Core M5
 
| family              = Core M5
Line 35: Line 36:
 
| isa                = x86-64
 
| isa                = x86-64
 
| microarch          = Skylake
 
| microarch          = Skylake
−
| platform            =  
+
| platform            = Skylake
 
| chipset            =  
 
| chipset            =  
 
| core name          = Skylake Y
 
| core name          = Skylake Y
Line 42: Line 43:
 
| core stepping      = D1
 
| core stepping      = D1
 
| process            = 14 nm
 
| process            = 14 nm
−
| transistors        =  
+
| transistors        = 1,750,000,000
 
| technology          = CMOS
 
| technology          = CMOS
−
| die size           =  
+
| die area           = 98.57 mm²
 +
| die width          = 9.57 mm
 +
| die length          = 10.3 mm
 
| word size          = 64 bit
 
| word size          = 64 bit
 
| core count          = 2
 
| core count          = 2
 
| thread count        = 4
 
| thread count        = 4
 
| max cpus            = 1
 
| max cpus            = 1
−
| max memory          = 16 GB
+
| max memory          = 16 GiB
  
 
| electrical          = Yes
 
| electrical          = Yes
Line 60: Line 63:
 
| ctdp up            = 7 W
 
| ctdp up            = 7 W
 
| ctdp up frequency  = 1500 MHz
 
| ctdp up frequency  = 1500 MHz
−
| temp max            = 100 °C
+
| tjunc min          = 5 °C
−
| temp min            = 0 °C
+
| tjunc max          = 100 °C
  
−
| packaging          = Yes
+
| package module 1 = {{packages/intel/fcbga-1515}}
−
| package             = FCBGA-1515
 
−
| package type        = FCBGA
 
−
| package pitch      = 0.4 mm
 
−
| package size        = 20 mm x 16.5 mm
 
−
| socket              = BGA-1515
 
−
| socket type        = BGA
 
 
}}
 
}}
−
The '''Core M5-6Y54''' is an ultra-low power dual-core {{arch|64}} [[x86]] microprocessor introduced by [[Intel]] in late 2015. This MPU operates at 1.1 GHz with a max turbo frequency of 2.7 GHz. This chip, which is manufactured in [[14 nm process]] based on the {{intel|Skylake}} microarchitecture and incorporates Intel's {{intel|HD Graphics 515}} Gen9 GPU clocked at 300 MHz with turbo frequency of 900 MHz.
+
'''Core M5-6Y54''' is an ultra-low power {{arch|64}} [[dual-core]] [[x86]] microprocessor introduced by [[Intel]] in late 2015. This MPU operates at 1.1 GHz with a max turbo frequency of 2.7 GHz. This chip, which is manufactured on a [[14 nm process]], is based on the {{intel|Skylake}} microarchitecture. The Core M5-6Y54 incorporates Intel's {{intel|HD Graphics 515}} Gen9 GPU clocked at 300 MHz with turbo frequency of 900 MHz.
  
 
== Cache ==
 
== Cache ==
 
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
 
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
−
{{cache info
+
{{cache size
 +
|l1 cache=128 KiB
 
|l1i cache=64 KiB
 
|l1i cache=64 KiB
 
|l1i break=2x32 KiB
 
|l1i break=2x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
−
|l1i extra=(per core)
 
 
|l1d cache=64 KiB
 
|l1d cache=64 KiB
 
|l1d break=2x32 KiB
 
|l1d break=2x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
−
|l1d extra=(per core)
+
|l1d policy=write-back
 
|l2 cache=512 KiB
 
|l2 cache=512 KiB
 
|l2 break=2x256 KiB
 
|l2 break=2x256 KiB
 
|l2 desc=4-way set associative
 
|l2 desc=4-way set associative
−
|l2 extra=(per core)
+
|l2 policy=write-back
 
|l3 cache=4 MiB
 
|l3 cache=4 MiB
 
|l3 break=2x2 MiB
 
|l3 break=2x2 MiB
−
|l3 extra=(shared LLC)
+
|l3 policy=write-back
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=LPDDR3-1866
 +
|ecc=No
 +
|max mem=16 GiB
 +
|controllers=1
 +
|channels=2
 +
|max bandwidth=27.81 GiB/s
 +
|bandwidth schan=13.91 GiB/s
 +
|bandwidth dchan=27.81 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 10
 +
| pcie config        = 1x4
 +
| pcie config 2      = 2x2
 +
| pcie config 3      = 1x2+2x1
 +
| pcie config 4      = 4x1
 
}}
 
}}
  
 
== Graphics ==
 
== Graphics ==
−
{{integrated graphic
+
{{integrated graphics
−
| gpu                = Intel HD Graphics 515
+
| gpu                = HD Graphics 515
 
| device id          = 0x191E
 
| device id          = 0x191E
 +
| designer            = Intel
 
| execution units    = 24
 
| execution units    = 24
−
| displays           = 3
+
| max displays       = 3
 +
| max memory          = 16 GiB
 
| frequency          = 300 MHz
 
| frequency          = 300 MHz
 
| max frequency      = 900 MHz
 
| max frequency      = 900 MHz
−
| max memory          = 16 GB
 
  
 
| output crt          =  
 
| output crt          =  
Line 112: Line 132:
 
| output dvi          = Yes
 
| output dvi          = Yes
  
−
| directx ver         = 12
+
| directx ver       = 12
−
| opengl ver         = 4.4
+
| opengl ver         = 4.4
−
| opencl ver         = 2.0
+
| opencl ver         = 2.0
−
| opengl es ver      =
+
| hdmi ver           = 1.4a
−
| hdmi ver           = 1.4a
+
| dp ver            = 1.2
−
| dvi ver            =
+
| edp ver           = 1.3
−
| dsi ver            =
+
| max res hdmi       = 4096x2304
−
| vulkan ver          =
+
| max res hdmi freq = 24 Hz
−
| dp ver              = 1.2
+
| max res dp         = 3840x2160
−
| edp ver             = 1.3
+
| max res dp freq   = 60 Hz
−
 
+
| max res edp       = 3840x2160
−
| max res hdmi       = 4096x2160
+
| max res edp freq   = 60 Hz
−
| max res hdmi freq   = 24 Hz
+
| max res vga       =  
−
| max res dvi         =
+
| max res vga freq  =  
−
| max res dvi freq    =
 
−
| max res dsi        =
 
−
| max res dsi freq    =
 
−
| max res dp          = 3840x2160
 
−
| max res dp freq     = 60 Hz
 
−
| max res dp 2       = 2880x1800
 
−
| max res dp 2 freq  = 60 Hz
 
−
| max res edp        = 3840x2160
 
−
| max res edp freq   = 60 Hz
 
−
| max res edp 2      = 2880x1800
 
−
| max res edp 2 freq  = 60 Hz
 
−
| max res vga         =  
 
−
| max res vga freq   =
 
−
 
 
−
| intel quick sync   = Yes
 
−
| intel intru 3d    = Yes
 
−
| intel insider      = Yes
 
−
| intel widi        = Yes
 
−
| intel fdi          = Yes
 
−
| intel clear video  = Yes
 
−
}}
 
−
 
 
−
== Memory controller ==
 
−
{{integrated memory controller
 
−
| type              = LPDDR3-1866
 
−
| type 1            = LPDDR3-1600
 
−
| controllers        = 1
 
−
| channels          = 2
 
−
| ecc support        = No
 
−
| max bandwidth      = 29.8 GB/s
 
−
| max memory        = 16 GB
 
−
}}
 
  
−
== Expansions ==
+
| features            = Yes
−
{{mpu expansions
+
| intel quick sync    = Yes
−
| pcie revision      = 3.0
+
| intel intru 3d      = Yes
−
| pcie lanes        = 10
+
| intel insider        =  
−
| pcie config        = 1x4
+
| intel widi          =  
−
| pcie config 1      = 2x2
+
| intel fdi            =  
−
| pcie config 2      = 1x2+2x1
+
| intel clear video    = Yes
−
| pcie config 3      = 4x16x1
+
| intel clear video hd = Yes
 
}}
 
}}
 +
{{skylake hardware accelerated video table|col=1}}
  
 
== Features ==  
 
== Features ==  

Revision as of 21:16, 3 June 2017

Template:mpu Core M5-6Y54 is an ultra-low power 64-bit dual-core x86 microprocessor introduced by Intel in late 2015. This MPU operates at 1.1 GHz with a max turbo frequency of 2.7 GHz. This chip, which is manufactured on a 14 nm process, is based on the Skylake microarchitecture. The Core M5-6Y54 incorporates Intel's HD Graphics 515 Gen9 GPU clocked at 300 MHz with turbo frequency of 900 MHz.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  2x2 MiB write-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR3-1866
Supports ECCNo
Max Mem16 GiB
Controllers1
Channels2
Max Bandwidth27.81 GiB/s
28,477.44 MiB/s
29.861 GB/s
29,860.76 MB/s
0.0272 TiB/s
0.0299 TB/s
Bandwidth
Single 13.91 GiB/s
Double 27.81 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes10
Configs1x4, 2x2, 1x2+2x1, 4x1


Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUHD Graphics 515
DesignerIntelDevice ID0x191E
Execution Units24Max Displays3
Max Memory16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
Frequency300 MHz
0.3 GHz
300,000 KHz
Burst Frequency900 MHz
0.9 GHz
900,000 KHz
OutputDP, eDP, HDMI, DVI
Max Resolution
HDMI4096x2304 @24 Hz
DP3840x2160 @60 Hz
eDP3840x2160 @60 Hz
Standards
DirectX12
OpenGL4.4
OpenCL2.0
DP1.2
eDP1.3
HDMI1.4a
Additional Features
Intel Quick Sync Video
Intel InTru 3D
Intel Clear Video
Intel Clear Video HD

Features

Template:mpu features

Drivers

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_m/m5-6y54&oldid=44124"
Facts about "Core m5-6Y54 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Core m5-6Y54 - Intel#io +
base frequency1,100 MHz (1.1 GHz, 1,100,000 kHz) +
bus typeDMI 3.0 +
clock multiplier11 +
core count2 +
core family6 +
core model78 +
core nameSkylake Y +
core steppingD1 +
designerIntel +
device id0x191E +
die area98.57 mm² (0.153 in², 0.986 cm², 98,570,000 µm²) +
die count2 +
die length10.3 mm (1.03 cm, 0.406 in, 10,300 µm) +
die width9.57 mm (0.957 cm, 0.377 in, 9,570 µm) +
drivers urlhttps://downloadcenter.intel.com/product/94026 +
familyCore m5 +
first announcedSeptember 1, 2015 +
first launchedSeptember 27, 2015 +
full page nameintel/core m/m5-6y54 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supportfalse +
has extended page tables supporttrue +
has featureHyper-Threading Technology +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Secure Key Technology +, Flex Memory Access +, Smart Response Technology +, My WiFi Technology +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Turbo Boost Technology 2.0 +, OS Guard +, Extended Page Tables +, Memory Protection Extensions + and Software Guard Extensions +
has intel enhanced speedstep technologytrue +
has intel flex memory access supporttrue +
has intel my wifi technology supporttrue +
has intel secure key technologytrue +
has intel smart response technology supporttrue +
has intel supervisor mode execution protectiontrue +
has intel turbo boost technology 2 0true +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
integrated gpuHD Graphics 515 +
integrated gpu base frequency300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu designerIntel +
integrated gpu execution units24 +
integrated gpu max frequency900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB) +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldateSeptember 27, 2015 +
main imageFile:skylake y (front).png +
manufacturerIntel +
market segmentMobile +
max cpu count1 +
max junction temperature373.15 K (100 °C, 212 °F, 671.67 °R) +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth27.81 GiB/s (28,477.44 MiB/s, 29.861 GB/s, 29,860.76 MB/s, 0.0272 TiB/s, 0.0299 TB/s) +
max memory channels2 +
max pcie lanes10 +
microarchitectureSkylake +
min junction temperature278.15 K (5 °C, 41 °F, 500.67 °R) +
model numberm5-6Y54 +
nameCore m5-6Y54 +
packageFCBGA-1515 +
part numberHE8066201930524 +
platformSkylake +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 281.00 (€ 252.90, £ 227.61, ¥ 29,035.73) +
s-specSR2EM +
sdp3 W (3,000 mW, 0.00402 hp, 0.003 kW) +
seriesm-6Y +
smp max ways1 +
supported memory typeLPDDR3-1866 + and DDR3L-1600 +
tdp4.5 W (4,500 mW, 0.00603 hp, 0.0045 kW) +
tdp down3.5 W (3,500 mW, 0.00469 hp, 0.0035 kW) +
tdp down frequency600 MHz (0.6 GHz, 600,000 kHz) +
tdp up7 W (7,000 mW, 0.00939 hp, 0.007 kW) +
tdp up frequency1,500 MHz (1.5 GHz, 1,500,000 kHz) +
technologyCMOS +
thread count4 +
transistor count1,750,000,000 +
turbo frequency (1 core)2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (2 cores)2,400 MHz (2.4 GHz, 2,400,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensionstrue +
x86/has software guard extensionstrue +