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Difference between revisions of "arm holdings/microarchitectures/cortex-a53"
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| designer = ARM Holdings | | designer = ARM Holdings | ||
| manufacturer = | | manufacturer = | ||
| − | | introduction = | + | | introduction = July 2014 |
| phase-out = | | phase-out = | ||
| − | | process = | + | | process = 28 nm |
| + | | process 2 = 20 nm | ||
| + | | process 3 = 16 nm | ||
| + | | process 4 = 14 nm | ||
| + | | process 5 = 10 nm | ||
| cores = 1 | | cores = 1 | ||
| cores 2 = 2 | | cores 2 = 2 | ||
Revision as of 19:37, 3 December 2016
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| Cortex-A53 µarch | |
| General Info |
Cortex-A53 (formerly Apollo) is a ultra-high efficiency microarchitecture designed by ARM Holdings as a successor to the Cortex-A9. The Cortex-A53, which implemented the ARMv8 ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on Cortex-A57) in big.LITTLE configuration to achieve better energy/performance.
Process Technology
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Architecture
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Die
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All Cortex-A53 Chips
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Facts about "Cortex-A53 - Microarchitectures - ARM"
| codename | Cortex-A53 + |
| core count | 1 +, 2 +, 3 + and 4 + |
| designer | ARM Holdings + |
| first launched | October 30, 2012 + |
| full page name | arm holdings/microarchitectures/cortex-a53 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8 + |
| manufacturer | TSMC +, Samsung + and GlobalFoundries + |
| microarchitecture type | CPU + |
| name | Cortex-A53 + |
| pipeline stages | 8 + |
| process | 40 nm (0.04 μm, 4.0e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) + |