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Difference between revisions of "arm holdings/microarchitectures/cortex-a53"
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(Created page with "{{armh title|Cortex-A53|arch}} '''Cortex-A53''' is a power-efficient microarchitecture] designed by ARM Holdings implementing the {{arm|ARMv8}} ISA. The A53 is typica...")
 
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{{armh title|Cortex-A53|arch}}
 
{{armh title|Cortex-A53|arch}}
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'''Cortex-A53''' is a power-efficient [[microarchitecture]]] designed by [[ARM Holdings]] implementing the {{arm|ARMv8}} ISA.
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{{microarchitecture
 +
| name          = Cortex-A53
 +
| designer      = ARM Holdings
 +
| manufacturer  =
 +
| introduction  =
 +
| phase-out    =
 +
| process      =
 +
| cores        = 1
 +
| cores 2      = 2
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| cores 3      = 3
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| cores 4      = 4
  
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The A53 is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance.
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| pipeline      = Yes
 +
| type          =
 +
| type 2        =
 +
| type N        =
 +
| OoOE          = No
 +
| speculative  = No
 +
| renaming      =
 +
| isa          = ARMv8
 +
| stages        = 8
 +
| stages min    =
 +
| stages max    =
 +
| issues        = 2
 +
 
 +
| inst          = Yes
 +
| feature      = Hardware virtualization
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| extension    = NEON
 +
| extension 2  = TrustZone
 +
| extension N  =
 +
 
 +
| cache        = Yes
 +
| l1i          = 8-64 KiB
 +
| l1i per      = core
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| l1i desc      = 2-way set associative
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| l1d          = 8-64 KiB
 +
| l1d per      = core
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| l1d desc      = 4-way set associative
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| l2            = 128 KiB - 2 MiB
 +
| l2 per        = cluster
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| l2 desc      = 16-way set associative
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| l3            =
 +
| l3 per        =
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| l3 desc      =
 +
 
 +
| core names      = <!-- Yes if specify -->
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| core name        =
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| core name 2      =
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| core name N      =
 +
 
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| succession      = Yes
 +
| predecessor      = Cortex-A9
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| predecessor link = arm_holdings/microarchitectures/cortex-a9
 +
| successor        =
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| successor link  =
 +
| successor 2      =
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| successor 2 link =
 +
}}
 +
'''Cortex-A53''' (formerly '''Apollo''') is a ultra-high efficiency [[microarchitecture]]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A9|l=arch}}. The Cortex-A53, implementing the {{arm|ARMv8}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance.

Revision as of 19:07, 3 December 2016

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Cortex-A53 µarch
General Info
ERROR: "atype" is missing!

Cortex-A53 (formerly Apollo) is a ultra-high efficiency microarchitecture] designed by ARM Holdings as a successor to the Cortex-A9. The Cortex-A53, implementing the ARMv8 ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on Cortex-A57) in big.LITTLE configuration to achieve better energy/performance.

Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/cortex-a53&oldid=30280"
Facts about "Cortex-A53 - Microarchitectures - ARM"
RDF feed
codenameCortex-A53 +
core count1 +, 2 +, 3 + and 4 +
designerARM Holdings +
first launchedOctober 30, 2012 +
full page namearm holdings/microarchitectures/cortex-a53 +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +, Samsung + and GlobalFoundries +
microarchitecture typeCPU +
nameCortex-A53 +
pipeline stages8 +
process40 nm (0.04 μm, 4.0e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) +