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Difference between revisions of "amd/athlon mp/amp1600dms3c"
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== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}} | {{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}} | ||
− | {{cache | + | {{cache size |
+ | |l1 cache=128 KiB | ||
|l1i cache=64 KiB | |l1i cache=64 KiB | ||
|l1i break=1x64 KiB | |l1i break=1x64 KiB | ||
|l1i desc=2-way set associative | |l1i desc=2-way set associative | ||
− | |l1i | + | |l1i policy= |
|l1d cache=64 KiB | |l1d cache=64 KiB | ||
|l1d break=1x64 KiB | |l1d break=1x64 KiB | ||
|l1d desc=2-way set associative | |l1d desc=2-way set associative | ||
− | |l1d | + | |l1d policy= |
|l2 cache=256 KiB | |l2 cache=256 KiB | ||
|l2 break=1x256 KiB | |l2 break=1x256 KiB | ||
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
− | |l2 | + | |l2 policy= |
− | |||
− | |||
− | |||
− | |||
}} | }} | ||
Revision as of 15:41, 26 November 2016
Template:mpu The Athlon MP 1600+ (OPN AMP1600DMS3C) based on the Palomino core was a 32-bit x86 multiprocessor developed by AMD and introduced in late 2001 for the server and workstation market. This MPU operated at 1.4 GHz with a FSB transfer rate of 266 MT/s (x10.5 multiplier). This processor, which was based on the K7 microarchitecture, was manufactured on a mature 180 nm copper interconnect technology at AMD's Fab 30 in Dresden, Germany.
Cache
- Main article: K7 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics
This MPU has no integrated graphics processing unit.
Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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- Advanced Configuration and Power Interface
- Halt State
- Stop Grant State
Documents
Datasheets
- AMD Athlon MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms; Publication # 25480 Rev: D; Issue Date: June 2002.
Others
- System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors; Publication # 25325; Rev: B; August 2002.
Facts about "Athlon MP 1600+ - AMD"
has amd smartmp technology | true + |
has feature | SmartMP Technology +, ACPI +, Halt State + and Stop Grant State + |
has multiprocessing support | true + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 2-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |