Revision as of 23:14, 7 May 2020

MAJ Gate

Typical Symbol

Functional

Truth Table

3-input Majority Gate Inputs Outputs A B C Q 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1

Other Gates Buffer TriBuffer NOT AND OR XOR NAND NOR XNOR Trans AOI OAI MAJ INH IMPLY NIMPLY

Other Components Plexers MUX DEMUX Encoder Decoder Pri-Encoder ALU Adder Subtractor Multiplier Divider Shifter Rotator MAC Comparator Negator Memory D latch D flip-flop SR latch JK flip-flop T flip-flop Register Register file SRAM Counter ROM CAM DRAM I/O Shift register SIPO PISO ADC DAC

The majority gate (MAJ gate) is a logic gate that implements the majority function - a device that outputs a HIGH when the majority of its inputs are HIGH, otherwise it outputs a LOW.

Applications

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MAJ3

A 3-input MAJ gate (MAJ3) can be implemented as .

CMOS

However the naive implementation will result in up to 30 transistors. Since

,

we can define MAJ3 as

and that can be implemented using a single AOI222 which is defined as

note that by substituting a, b, and c for d, e, and f we get MAJ:

It can also be implemented using a OAI222 gate the very same way. Since

,

then

MAJ5

A MAJ5 can be naively described as the OR of 10 MAJ3 gates. It can be simplified down to 10 AND gates and 9 OR gates by rewriting the terms.^[1] This is probably optimal, since the optimal sorting network of 5 terms has 9 comparisons.

See also

• logic gates
• compound logic gates