From WikiChip
Difference between revisions of "intel/microarchitectures/tiger lake"
< intel‎ | microarchitectures

(Created page with "{{intel title|Tigerlake|arch}} {{microarchitecture | name = Tigerlake | manufacturer = Intel | introduction = 2019-2020 | phase-out = | process...")
 
(No difference)

Revision as of 23:35, 14 April 2016

Edit Values
Tigerlake µarch
General Info
ERROR: "atype" is missing!

Tigerlake is a planned microarchitecture by Intel as a successor to Icelake. Tigerlake is expected to be fabricated using a 7 nm or 10 nm process.

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/tiger_lake&oldid=16877"
Facts about "Tiger Lake - Microarchitectures - Intel"
RDF feed
codenameTiger Lake +
core count2 +, 4 +, 6 + and 8 +
designerIntel +
first launchedSeptember 2, 2020 +
full page nameintel/microarchitectures/tiger lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameTiger Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process10 nm (0.01 μm, 1.0e-5 mm) +